Image sensor with dummy pixel or dummy pixel array

• US 6,344,877 B1
• Filed: 06/12/1997
• Issued: 02/05/2002
• Est. Priority Date: 06/12/1997
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Shin, Hyun Jong, Wong, Hon-Sum Philip, Yang, Jungwook, Gowda, Sudhir Muniswamy, Xiao, Peter Hong
• Primary Examiner(s): CHRISTENSEN, ANDREW BRUCE
• Application Number:
  US08/873,539
• Time in Patent Office: 1,699 Days
• Field of Search: 348/241, 348/243, 348/245, 348/248, 348/251, 348/300, 348/301, 348/302, 348/307, 348/308, 378/98.2, 257/291, 257/292, 250/208.1
• US Class Current: 348/245
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/63 applied to dark current
• CPC Class Codes: H04N 25/671 for non-uniformity detection or correction
• CPC Class Codes: H04N 25/673 by using reference sources
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

Disclosed is an image sensor including one or more dummy pixels that produce a reference signal which is used to compensate for errors within the devices of the main pixel cells. In one embodiment, at least one dummy pixel is used in conjunction with other circuitry to correct for nonlinearities in the transfer characteristic of a source follower transistor within each pixel. In another embodiment, an array of dummy pixels is used to correct for leakage current within the pixels during an electronic shutter mode of operation. The two techniques can be combined whereby both threshold voltage mismatch and leakage current are compensated for.

Claims

1. An image sensor, comprising:

a plurality of imager cells arranged in rows and columns, with the imager cells of a particular column being coupled to a column data line of that column, and each imager cell being operable to selectively provide an output signal indicative of one of an amount of light incident upon that imager cell and an amount of noise due to non-ideal characteristics of said each imager cell;

at least one dummy pixel having a source follower field effect transistor and characteristics which are at least similar to characteristics of said each imager cell, said dummy pixel providing an output reference signal; and

correlated double sampling circuitry for performing a noise sampling and a signal sampling with respect to said output signal from said each imager cell in association with said output reference signal from said dummy pixel, and image data corresponding to said each imager cell being obtained from said noise sampling and signal sampling,

wherein said correlated double sampling circuitry comprises a plurality of comparators, each having a first input terminal coupled to one of said column data lines and a second input terminal connected to receive said output reference signal, and

wherein said reference signal is a time varying reference signal and further comprising a plurality of up/down counters, each coupled to an output of one of said comparators and operable to count in a first direction during a first sampling interval and in an opposite direction during a second sampling interval, each up/down counter being responsive to an output of the associated comparator to stop counting when the amplitude of the time varying reference signal substantially equals the amplitude of a reset level in the first sampling interval and a signal level in the second sampling interval to thereby complete a correlated double sampling operation.

2. The image sensor of claim 1, wherein said dummy pixel characteristics are substantially identical to characteristics of each imager cell.

3. The image sensor of claim 1, further comprising a plurality of registers, each coupled to an output of one of said comparators, for temporarily storing a first digital code corresponding to a reset level and a second digital code corresponding to a signal level of an activated pixel, each said register being latched by a predetermined output level of the associated comparator, each register subsequently transferring each of said first digital codes to subtraction circuitry for subtracting each of said first digital codes from a corresponding second digital code.

4. The image sensor of claim 1, wherein said reference signal is a time varying reference signal and further including means for ramping said time varying reference signal from a maximum level to a first minimum level during a first sampling interval, and from said maximum level to a second minimum level lower than said first minimum level during a second sampling interval in connection with a correlated double sampling operation.

5. The image sensor of claim 1, wherein:

each imager cell includes a photosensitive element for providing a photocharge responsive to incident light, circuit means for selectively transferring the photocharge to a reference node within the imager cell, and a reset switch operable to selectively switch a low supply voltage to the reference node to isolate the reference node from the associated column data line.

6. The image sensor of claim 1, including complementary metal oxide semiconductor (CMOS) circuitry for providing timing and control signals to the imager cells.

7. The image sensor of claim 1, wherein each imager cell comprises:

a photosensitive element providing a photocharge responsive to incoming light;

a first transistor coupled to a row select line carrying a row select signal to imager cells of a common row to selectively activate the imager cells of the common row for image data readout, said first transistor operable to transfer said photocharge towards a reference circuit node within said imager cell responsive to said row select signal;

a second transistor operably coupled to said first transistor, said second transistor operative to selectively set a voltage level at said reference node; and

a third transistor having a control terminal coupled to said reference node, and an output terminal coupled to the column data line of the column associated with the particular imager cell, said third transistor providing a first output indicative of a reset potential of said reference node during a first sampling interval in which said first and second transistors are both off, and a signal output indicative of potential of said reference node during a second sampling interval.

8. The image sensor of claim 1, wherein said non-ideal characteristics include leakage current within each imager cell, each imager cell includes a shutter transistor to perform an electronic shuttering function, and said at least one dummy pixel comprises an array of dummy pixels coupled to a common output data line, each dummy pixel selectively providing an output signal on said common data line related to leakage current therein and also related to leakage current within associated ones of said pixels, said output signals on said common data line being used to reduce errors in said image data due to leakage current.

9. The image sensor of claim 8, wherein said array of dummy pixels comprises a column of dummy pixels disposed adjacent to said columns of imager cells and connected to common supply voltage lines as said imager cells.

10. An image sensor comprising:

a plurality of imager cells arranged in rows and columns, with the imager cells within any given column being coupled to a column data line of that column, and each imager cell having a source follower transistor, said imager cell operable to selectively provide a first output during a first sampling interval indicative of a reset level and a second output during a second sampling interval indicative of an amount of light incident upon that imager cell;

a plurality of dummy imager cells operative to compensate for leakage current due to non-ideal characteristics of each imager cell within said imager cells;

at least one dummy pixel having a source follower transistor, said dummy pixel operative to compensate for threshold voltage variation due to non-ideal characteristics of each imager cell occurring within said source follower transistor of each of said imager cells; and

correlated double sampling circuitry coupled to said column data lines for providing correlated double sampled image data with said leakage current and threshold voltage variation compensated for, wherein said non-ideal characteristics include nonlinear voltage transfer characteristics of said source follower transistor within each imager cell,

wherein said dummy pixel comprises a source follower field effect transistor, a resistor connected to a gate of said transistor and a further transistor having a first conducting terminal coupled to said resistor, a second conducting terminal coupled to receive a supply voltage and a control terminal coupled to receive a control voltage, wherein the connection between said resistor and said gate terminal define a reference circuit node having a potential that is caused to vary during said first and second sampling intervals.

11. The image sensor of claim 10 wherein:

said plurality of dummy imager cells are arranged in an array, each dummy imager cell is connected to a common output data line and providing an output indicative of leakage current of imager cells in an associated row on said output data line when the associated row of imager cells is activated;

said image sensor further comprising a unidirectional counter and a digital to analog (D/A) converter coupled to said counter and to said dummy pixel, said counter operative to count during each of said first and second sampling intervals and said D/A converter providing a ramped reference signal output during each sampling interval;

said image sensor comprising circuitry operatively coupled to said output data line and to said D/A converter for modifying said ramped reference signal in accordance with said output indicative of leakage current; and

said dummy pixel providing a dummy pixel output related to said modified ramped reference signal, said dummy pixel output including compensation for threshold voltage variation and being provided to said correlated double sampling circuitry.