Repair analysis circuit for redundancy, redundant repairing method, and semiconductor device

• US 6,345,004 B1
• Filed: 12/26/2000
• Issued: 02/05/2002
• Est. Priority Date: 07/21/2000
• Status: Expired due to Term

• Current Assignee: Renesas Semiconductor Manufacturing Co. Ltd. (Renesas Electronics Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Ryoden Semiconductor System Engineering Corporation
• Inventors: Sugiura, Kazushi, Komoike, Tatsunori, Omura, Ryuji
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US09/745,421
• Publication Number:
  US 20020008998A1
• Time in Patent Office: 406 Days
• Field of Search: 365/200, 365/201, 365/230.03, 714/6
• US Class Current: 365/200
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells

Abstract

A repair analysis circuit for redundancy, a redundant method for repairing a redundant, and a semiconductor device that can shorten time for testing defective memory cells, that eliminate the need of failure memories having a huge capacity for storing defective bits to make the testing apparatus inexpensive, and that easily cope with increase and decrease in IO numbers. A large number of IO outputs MOUT are collectively compared with a specified expected value, and as a result resultant judgment information DOUT is outputted to an error information acquiring device 22, and an analyzing device 23 reads table information sequentially from each block to obtain replacing data, and the replacing data are outputted serially to the external tester through the external I/F circuit 24. The redundant memory cell 4a itself can be made to compare with a specified expected value in the same manner as other memory cells 4 or the like. By outputting the result of determination can also be outputted to the error information acquiring device 22 in the same manner as judgment information DOUT for other memory cells 4 or the like, repair analysis can be performed without using any defective redundant memory cells.

Claims

1. A repair analysis circuit for redundancy for repairing defective memory cells in a semiconductor memory device, said semiconductor memory device comprising memory cells arranged in a matrix, and redundant memory cells arranged in the row and/or column direction of said memory cells, said repair analysis circuit for redundancy comprising:

an error information acquiring portion provided in each predetermined block of said memory cells, said error information acquiring portion stores judgement information including defective information that contains the address of the defective memory cell in said block and the output from said defective memory cell, and the candidate address of the redundant memory cell that repairs said defective memory cell, and

an analyzing portion sequentially inputting the judgement information stored in said error information acquiring portions into each of said error information acquiring portions, and obtaining the redundant memory cell that repairs the defective memory cell for each of said predetermined blocks.

2. The repair analysis circuit for redundancy according to claim 1, wherein the judgement information stored in said error information acquiring portion further comprises the address of the defective memory cell in said redundant memory cells and the output from said defective memory cell, and

said analyzing portion sequentially inputs the judgement information into each of said error information acquiring portions, and obtains redundant memory cells that repair the defective memory cell for each of said predetermined blocks, other than the defective memory cells in said redundant memory cells.

3. The repair analysis circuit for redundancy according to claim 1, wherein said analyzing portion is disposed underneath the row address decoder in said semiconductor memory device, but not underneath said memory cells and said redundant cells.

4. The repair analysis circuit for redundancy according to claim 1, wherein said analyzing portion comprises pins for inputting at least clock signals, command input permitting signals, command signals and pins for serially outputting repair information signals related to the redundant memory cell to be repaired to the outside.

5. A semiconductor device, comprising:

a semiconductor memory device having memory cells arranged in a matrix, and redundant memory cells arranged in the row and/or column direction of said memory cells;

a judging circuit disposed in each specified block of said memory cells for comparing data outputted from said block with a specified expected value; and

outputting judgement information comprising defect information that contains the address of a defective memory cell in said block and the output from said defective memory cell, and the address of the candidate redundant memory cell that repairs said defective memory cell, and

a repair analysis circuit for redundancy for repairing said defective memory cell in said semiconductor memory device, said repair analysis circuit for redundancy, having;

error information acquiring portions that store judgment information outputted from said judgment circuit; and

an analyzing portion that inputs defect information stored in each of said error information acquiring portions and the address of the candidate redundant memory cell sequentially, and obtains a redundant memory cell to repair defective memory cells in each of said specified blocks.

6. The semiconductor device according to claim 5, further comprising a pattern generator that generates a specified expected value, and outputs said expected value to said judgment circuit.

7. A redundant repairing method for repairing defective memory cells in a semiconductor memory device having memory cells arranged in a matrix, and redundant memory cells arranged in the row and/or column direction of said memory cells, comprising the steps of:

an expected value generating of making a pattern generator generate a specified expected value;

a judgment of comparing data outputted from a specified block of said memory cell with the expected value generated in said step of expected value generating, and outputting judgement information having defect information that contains the address of a defective memory cell in said block and the output from said defective memory cell, and the address of a candidate redundant memory cell to repair said defective memory cell;

an error information acquiring of storing judgment information outputted in said step of judgment in each of said specified blocks; and

an analyzing of sequentially inputting judgment information in each of said specified blocks stored in said step of error information acquiring, and determining the redundant memory cell to repair the defective memory cell in each of said specified blocks.

8. The redundant repairing method according to claim 7, wherein said judgment information outputted in said step of judgment further contains the address of a defective memory cell in said redundant memory cell, and the output from said defective memory cell, and

said step of analyzing inputs said judgment information in each of said blocks sequentially, and determines a redundant memory cell that repairs defective memory cells in each of said blocks from said redundant memory cells other than defective memory cells.