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Repair analysis circuit for redundancy, redundant repairing method, and semiconductor device

  • US 6,345,004 B1
  • Filed: 12/26/2000
  • Issued: 02/05/2002
  • Est. Priority Date: 07/21/2000
  • Status: Expired due to Term
First Claim
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1. A repair analysis circuit for redundancy for repairing defective memory cells in a semiconductor memory device, said semiconductor memory device comprising memory cells arranged in a matrix, and redundant memory cells arranged in the row and/or column direction of said memory cells, said repair analysis circuit for redundancy comprising:

  • an error information acquiring portion provided in each predetermined block of said memory cells, said error information acquiring portion stores judgement information including defective information that contains the address of the defective memory cell in said block and the output from said defective memory cell, and the candidate address of the redundant memory cell that repairs said defective memory cell, and an analyzing portion sequentially inputting the judgement information stored in said error information acquiring portions into each of said error information acquiring portions, and obtaining the redundant memory cell that repairs the defective memory cell for each of said predetermined blocks.

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