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Shift register

  • US 6,345,085 B1
  • Filed: 11/06/2000
  • Issued: 02/05/2002
  • Est. Priority Date: 11/05/1999
  • Status: Expired due to Term
First Claim
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1. A shift register including a plurality of stages which are commonly connected to a high-level voltage source, a low-level voltage source and a phase-delayed clock signal generator and individually connected to row lines and are connected, in cascade, with respect to a scanning signal so as to charge and discharge each of the row lines, each stage of the shift register comprising:

  • an output circuit including a pull-up transistor having a first input electrode for receiving a first clock signal, a first output electrode connected to the row line and a first control electrode, and a pull-down transistor having a second input electrode connected to the low-level voltage source, a second output electrode connected to the row line and a second control electrode;

    an input circuit for generating a first control signal to be applied to the first control electrode and for generating a second control signal to be applied to the second control electrode in response to a second clock signal having a phase different from the first clock signal; and

    a first capacitor means connected between the input circuit and the row line, a second capacitor means connected between the second control electrode and the low-level voltage source, and a third capacitor means connected between the first control electrode and the low-level voltage source, at least one of the first to third capacitor means including at least two capacitors connected in series.

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