Shift register

• US 6,345,085 B1
• Filed: 11/06/2000
• Issued: 02/05/2002
• Est. Priority Date: 11/05/1999
• Status: Expired due to Term

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Kim, Jin Sang, Yeo, Ju Cheon
• Primary Examiner(s): RUBIN, MARGARET R
• Application Number:
  US09/705,714
• Time in Patent Office: 456 Days
• Field of Search: 377/54, 377/75
• US Class Current: 377/54
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

A shift register for driving a pixel array is adapted to prevent a defect due to a short of a capacitor. In each stage of the shift register, an output circuit is provided with a pull-up transistor having a first input electrode for receiving a first clock signal, a first output electrode connected to a row line and a first control electrode, and a pull-down transistor having a second input electrode connected to a low-level voltage source, a second output electrode connected to the row line and a second control electrode. An input circuit generates a first control signal to be applied to the first control electrode and a second control signal to be applied to the second control electrode in response to a second clock signal having a phase different from the first clock signal. A first capacitor is connected between the input circuit and the row line, a second capacitor is connected between the second control electrode and the low-level voltage source, and a third capacitor is connected between the first control electrode and the low-level voltage source. At least one of the first to third capacitors has associated therewith a second capacitor connected in series thereto.

Claims

1. A shift register including a plurality of stages which are commonly connected to a high-level voltage source, a low-level voltage source and a phase-delayed clock signal generator and individually connected to row lines and are connected, in cascade, with respect to a scanning signal so as to charge and discharge each of the row lines, each stage of the shift register comprising:

an output circuit including a pull-up transistor having a first input electrode for receiving a first clock signal, a first output electrode connected to the row line and a first control electrode, and a pull-down transistor having a second input electrode connected to the low-level voltage source, a second output electrode connected to the row line and a second control electrode;

an input circuit for generating a first control signal to be applied to the first control electrode and for generating a second control signal to be applied to the second control electrode in response to a second clock signal having a phase different from the first clock signal; and

a first capacitor means connected between the input circuit and the row line, a second capacitor means connected between the second control electrode and the low-level voltage source, and a third capacitor means connected between the first control electrode and the low-level voltage source, at least one of the first to third capacitor means including at least two capacitors connected in series.

2. The shift register according to claim 1, wherein each of the first to third capacitor means includes at least two capacitors connected in series.

3. The shift register according to claim 1, wherein each of the first and third capacitor means includes only one capacitor, and wherein the second capacitor means includes at least two capacitors connected in series.

4. The shift register according to claim 1, wherein each of the serially connected capacitors further comprises:

at least two electrode layers and an insulating layer disposed alternately on a substrate.

5. The shift register according to claim 1, wherein each of the serially connected capacitors further includes:

a first electrode layer provided on a substrate;

an insulating layer covering the first electrode layer; and

at least two second electrode layers provided on the insulating layer, said two second electrode layers being disposed in a same plane so as to be opposed to the first electrode layer.

6. A shift register including a plurality of stages which are commonly connected to a high-level voltage source, a low-level voltage source and a phase-delayed clock signal generator and individually connected to row lines and are connected, in cascade, with respect to a scanning signal so as to charge and discharge each of the row lines, each stage of the shift register comprising:

an output circuit including a pull-up transistor having a first input electrode for receiving a first clock signal, a first output electrode connected to the row line and a first control electrode, and a pull-down transistor having a second input electrode connected to the low-level voltage source, a second output electrode connected to the row line and a second control electrode;

an input circuit for generating a first control signal to be applied to the first control electrode and for generating a second control signal to be applied to the second control electrode in response to a second clock signal having a phase different from the first clock signal; and

a first capacitor means connected between an intermediate terminal and the row line, a second capacitor means connected between the second control electrode and the low-level voltage source, a third capacitor means connected between the intermediate terminal and the low-level voltage source, and a fourth capacitor means connected between the first capacitor and the input circuit, at least one of the first to fourth capacitor means including at least two capacitors connected in series.

7. The shift register according to claim 6, wherein each of the first, third and fourth capacitor means includes one capacitor, and wherein the second capacitor means includes at least two capacitors connected in series.

8. A shift register comprising a plurality of stages, each of said stages being commonly connected to a high-level voltage source, a low-level voltage source and a phase-delayed clock signal generator, and being individually connected to a corresponding one of a plurality of row lines, and said stages being connected, in cascade, with respect to a scanning signal so as to charge and discharge each of the row lines, each of said stages comprising:

an output circuit having a first input electrode for receiving a first clock signal, a second input electrode connected to the low-level voltage source, an output connected to the corresponding row line, and first and second control electrodes;

an input circuit for generating a first control signal to be applied to the first control electrode and for generating a second control signal to be applied to the second control electrode in response to a second clock signal having a phase different from the first clock signal; and

a first capacitor connected between the first control electrode and the corresponding row line, a second capacitor connected between the second control electrode and the low-level voltage source, a third capacitor connected between the first control electrode and the low-level voltage source, and a fourth capacitor connected in series to one of the first, second and third capacitors.

9. The shift register of claim 8, wherein the output circuit comprises:

a pull-up transistor having connected to the first input electrode and the first control electrode, and having a first output electrode connected to the row line; and

a pull-down transistor connected to the second input electrode and second control electrode and having a second output electrode connected to the row line.

10. The shift register of claim 8, further comprising a fifth capacitor connected in series to a second one of the first, second and third capacitors.

11. The shift register of claim 10, further comprising a sixth capacitor connected in series to a third one of the first, second and third capacitors.

12. The shift register of claim 8, wherein the capacitors connected in series further comprise:

a first electrode layer formed on a substrate;

a first insulating layer formed immediately on the first electrode layer;

a second electrode layer formed immediately on the first insulating layer;

a second insulating layer formed immediately on the second electrode layer; and

a third electrode layer formed immediately on the second insulating layer.

13. The shift register of claim 12, wherein the third electrode layer is a transparent electrode layer.

14. The shift register of claim 8, wherein the capacitors connected in series further comprise:

a first electrode layer provided on a substrate;

an insulating layer covering the first electrode layer; and

at least two second electrode layers provided on the insulating layer, said two second electrode layers being disposed in a same plane so as to be opposed to the first electrode layer.