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Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line

  • US 6,345,342 B1
  • Filed: 11/09/1999
  • Issued: 02/05/2002
  • Est. Priority Date: 11/09/1999
  • Status: Expired due to Term
First Claim
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1. A method of maintaining cache coherency in a computer system having a plurality of processing units, each processing unit having at least one cache, comprising the steps of:

  • storing a modified value corresponding to a memory block of a system memory device into a first cache line of a first cache of a first processing unit and assigning a first coherency state to the first cache line indicating that the first cache line contains the modified value;

    issuing a read request from a second cache of a second processing unit for an address associated with the memory block, wherein said read request includes a programmably controlledflag indicating whether the first cache should deallocate the first cache line upon sourcing the modified value to the second cache;

    setting the flag to indicate that the first cache should deallocate the first cache line;

    sourcing the modified value from the first cache line to a second cache line of the second cache;

    deallocating the first cache line; and

    assigning a second coherency state to the second cache line indicating that the second cache line contains the value as modified by another processing unit and that the modified value has not been written to the memory block of the system memory device.

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