Fault-tolerant access to storage arrays using active and quiescent storage controllers

• US 6,345,368 B1
• Filed: 01/15/1999
• Issued: 02/05/2002
• Est. Priority Date: 03/31/1997
• Status: Expired due to Term

• Current Assignee: NetApp, Inc.
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Bergsten, James R.
• Primary Examiner(s): Nguyen, Hiep T.
• Application Number:
  US09/231,245
• Time in Patent Office: 1,117 Days
• Field of Search: 711/162, 711/114, 714/4, 714/11, 707/204
• US Class Current: 714/11
• CPC Class Codes: G06F 11/201 between storage system components
• CPC Class Codes: G06F 11/2058 using more than 2 mirrored copies
• CPC Class Codes: G06F 11/2069 Management of state, configuration or failover
• CPC Class Codes: G06F 11/2071 using a plurality of controllers
• CPC Class Codes: G06F 11/2094 Redundant storage or storage space G06F11/2056 takes precedence
• CPC Class Codes: G06F 11/2097 maintaining the standby controller/processing unit updated initialisation or re-synchronisation thereof G06F11/1658 and subgroups
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD
• CPC Class Codes: Y10S 707/99953 Recoverability
• CPC Class Codes: Y10S 707/99954 Version management
• CPC Class Codes: Y10S 707/99955 Archiving or backup

Abstract

A network comprises at least one host processing system, a number of storage controllers, each coupled to one of a plurality of storage arrays, each storage array including at least one mass storage device. Each storage controller may be couple to at least one host processing system and to at least one other storage controller to control access of the host processing systems to the mass storage devices. Multiple copies of data are maintained in storage arrays that are geographically remote to each other, such that any copy can be accessed by any host. Each storage controller includes an interface with a host that emulates a mass storage device and an interface with a local storage array that emulates a host. The interfaces to the host and local storage arrays are independent of the type of host or devices in the local storage array. Two or more hosts may be dissimilar to each other, and two or more storage arrays may include dissimilar mass storage devices. Hosts access stored data using virtual addressing. During a data access, the storage controller connected to the accessing host maps a virtual address provided by the host to a real physical location in any of the storage arrays, such that the actual location of the data is transparent to the host. The storage controllers provide automatic back-up and error correction as well as write protection of back-up copies.

Claims

1. A storage controller comprising:

a processor; and

a memory accessible to the processor and having sequences of instructions stored therein which configure the storage controller to selectively operate in either an active mode or a quiescent mode, such that the storage controller is configured to provide a host processing system with access to a storage array when in the active mode, and such that the storage controller is further configured to, when in the quiescent mode, monitor the status of an active storage controller, the active storage controller providing the host processing system with access to the storage array, and respond to a failure of the active storage controller by automatically switching to the active mode.

2. A storage controller according to claim 1, further comprising:

a first interface with the host processing systems for emulating the storage array; and

a second interface with the storage array for emulating the host processing system.

3. A storage controller according to claim 1, further comprising a port for communicating with a remote active storage controller.

4. A storage controller according to claim 1, wherein the memory further comprises sequences of instructions which further configure the storage controller to, when in the quiescent mode:

receive a write request, the write request having write data associated therewith; and

respond to the write request by caching the write data; and

provide an acknowledgement to the active storage controller that the write data has been cached.

5. A storage controller according to claim 1, wherein the memory further comprises sequences of instructions which further configure the storage controller to, when in the active mode:

receive a write request from the host processing system, the write request having write data associated therewith;

cause the write data to be stored in the storage array; and

signal completion of the write request to the host processing system only after receiving an acknowledgement from a quiescent storage controller that the write data has been cached by the quiescent storage controller.

6. A quiescent storage controller operable to provide a host processing system with access to a storage device, the quiescent storage controller comprising:

a processor;

a first port for communicating with an active storage controller, the active storage controller providing the host processing system with access to the storage device; and

a memory accessible to the processor and having sequences of instructions stored therein which configure the quiescent storage controller to;

use the first port to monitor a status of the active storage controller;

respond to a failure of the active storage controller by automatically assuming an active status and operating in substitution for the active storage controller.

7. A quiescent storage controller according to claim 6, further comprising:

a first interface with the host processing systems for emulating the storage device; and

a second interface with the storage device for emulating the host processing system.

8. A quiescent storage controller according to claim 6, further comprising a second port for communicating with a remote active storage controller.

9. A quiescent storage controller according to claim 6, wherein the memory further comprises sequences of instructions which configure the quiescent storage controller to:

receive a writ e request, the write request having write data associated therewith; and

respond to the write request by caching the write data; and

provide an acknowledgement to the active storage controller that the write data has been cached.

10. A quiescent storage controller according to claim 9, wherein the first active storage controller is further configured to provide an acknowledgement of the write request to the host processing system in response to receiving an acknowledgement from the quiescent storage controller that the write data has been cached.

11. A quiescent storage controller according to claim 10, wherein the first active storage controller is further configured to signal the quiescent storage controller to release the cached write data in response to writing the data successfully to the first storage array.

12. A storage controller comprising:

means for receiving a request from a host processing system to perform a write operation to store data in a storage device;

means for causing the data to be stored in the storage device in response to the request;

means for waiting for a signal from a second storage controller indicating that the second storage controller has cached the data in response to the request; and

means for acknowledging the write operation to the host processing system only after receiving the signal indicating that the second storage controller has cached the data.

13. A storage controller according to claim 12, further comprising means for signaling the second storage controller to release the cached data only after receiving an indication from the storage device that the data has been stored in the storage device.

14. A storage controller comprising:

means for emulating a storage device to a host processing system;

means for emulating the host processing system to the storage device;

means for enabling the storage controller to operate in either an active mode or a quiescent mode;

means for monitoring the status of an active storage controller when in the quiescent mode, the active storage controller providing the host processing system with access to the storage array;

means for automatically switching to the active mode in response to detecting a failure of the active storage controller; and

means for providing the host processing system with access to the storage device when in the active mode.

15. A storage controller according to claim 14, further comprising means for communicating with a remote active storage controller when in the active mode.

16. A storage controller according to claim 14, further comprising:

means for receiving a write request associated with the host processing system, the write request having write data associated therewith; and

means for caching the write data in response to the write request when in the quiescent mode; and

means for provide an acknowledgement to the active storage controller that the write data has been cached.

17. A storage controller according to claim 16, further comprising:

means for causing the write data to be stored in the storage device only when in the active mode; and

means for acknowledging the write request to the host processing system when in the active mode only after receiving a signal from a quiescent storage controller that the write data has been cached by the quiescent storage controller.

18. A system comprising:

a host processing system;

a storage array;

a first active storage controller coupled to the host processing system and the storage array;

a second active storage controller coupled to the first active storage controller;

a second storage array coupled to the second active storage controller; and

a quiescent storage controller coupled to the first active storage controller by a private communication channel, the quiescent storage controller including means for automatically operating as an active storage controller in place of the first active storage controller in response to a failure of the first active storage controller.

19. A system according to claim 18, wherein the quiescent storage controller further comprises:

means for receiving a write request based on a write request from the host processing system, the write request associated with write data; and

means for caching the write data in response to the write request.

20. A system according to claim 19, wherein the first active storage controller comprises means for providing an acknowledgement of the write request to the host processing system only after receiving an acknowledgement from the quiescent storage controller that the write data has been cached.

21. A system according to claim 20, wherein the first active storage controller comprises means for signaling the quiescent storage controller to release the cached write data in response to writing the data successfully to the first storage array.

22. A system comprising:

a plurality of host processing systems;

a plurality of storage arrays;

a plurality of active storage controllers, each of the active storage controllers coupled to one of the host processing systems, one of the storage arrays, and another one of the active storage controllers, each of the active storage controllers having a first interface with one of the host processing systems for emulating a mass storage device, each of the active storage controllers further having a second interface with a local storage array for emulating a host processing system, the plurality of active storage controllers cooperating to permit any of the host processing systems to access data stored in any of the storage arrays; and

a quiescent storage controller coupled to a first one of the storage controllers by a private communication channel, the quiescent storage controller configured to automatically operate as an active storage controller in response to detecting a failure of the first one of the active storage controllers.

23. A system according to claim 22, wherein the first one of the active storage controllers is configured to provide a signal to the quiescent storage controller in response to a successful data write by the active storage controller.

24. A system according to claim 22, wherein the quiescent storage controller is further configured to receive a write request from a first one of the host processing systems the write request having write data associated therewith, and to respond to the write request by caching the write data.

25. A system according to claim 24, wherein the first one of the active storage controllers is further configured to provide an acknowledgement of the write request to the first one of the host processing systems in response to receiving an acknowledgement from the quiescent storage controller that the write data has been cached.

26. A system according to claim 25, wherein the first one of the active storage controllers is further configured to signal the quiescent storage controller to release the cached write data in response to writing the data successfully to a first one of the storage arrays.

27. A method of operating a storage controller, the method comprising:

receiving a request from a host processing system to perform a write operation to store data in a storage device;

causing the data to be stored in the storage device in response to the request;

waiting for a signal from a second storage controller indicating that the second storage controller has cached the data in response to the request; and

acknowledging the write operation to the host processing system only after receiving the signal indicating that the second storage controller has cached the data.

28. A method according to claim 27, further comprising signaling the second storage controller to release the cached data only after receiving an indication from the storage device that the data has been stored in the storage device.

29. A method of operating a storage controller, the method comprising:

monitoring a status of an active storage controller while in a quiescent mode, the active storage controller providing a host processing system with access to a storage array; and

in response to detecting a failure of the active storage controller, automatically switching from the quiescent mode to an active mode to substitute for the active storage controller, including;

emulating the storage device to the host processing system; and

emulating the host processing system to the storage device.

30. A method according to claim 29, further comprising communicating with a remote active storage controller when in the active mode.

31. A method according to claim 29, further comprising, while in the quiescent mode:

receiving a write request originating from the host processing system, the write request having write data associated therewith;

caching the write data; and

providing an acknowledgement to the active storage controller that the write data has been cached.