Method of performing diagnostic procedures on a queue structure

• US 6,345,371 B1
• Filed: 05/05/1999
• Issued: 02/05/2002
• Est. Priority Date: 05/05/1999
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Lam, Ian
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): TORRES, JOSEPH D
• Application Number:
  US09/304,958
• Time in Patent Office: 1,007 Days
• Field of Search: 714/718, 714/719, 714/824, 714/735, 714/712
• US Class Current: 714/719
• CPC Class Codes: G06F 11/2273 Test methods
• CPC Class Codes: G06F 11/25 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G11C 29/003 in serial memories
• CPC Class Codes: H04L 43/50 Testing arrangements

Abstract

A method and apparatus are disclosed for testing the functionality of a queue structure. An input circuit is provided for inputting data into an input portion of the queue structure, while an output circuit is provided for retrieving data from an output portion of the queue structure. A comparison logic circuit compares the retrieved data with the input data to determine the integrity of the data that was stored in the queue structure and verify that the data from the output portion is identical to the data input to the queue. Various embodiments are disclosed for testing queue structure both in real time and in a test mode.

Claims

1. A method of testing the functionality of a queue structure that queues entries, the method comprising the steps:

inputting data into an input portion of the queue structure;

transferring the data into an output portion of the queue structure;

retrieving the data from the output portion of the queue structure; and

comparing the retrieved data with the input data to determine the integrity thereof by verifying that the input data has not been altered within the queue structure;

wherein the integrity of the data indicates the functionality of the queue structure.

2. The method of claim 1 further comprising the step of inputting the retrieved data back into the input portion of the queue structure.

3. The method of claim 1, wherein:

the step of inputting data includes the step of inputting data from prescribed fields of a forwarding descriptor onto a port vector index bus of the input portion of the queue; and

the step of retrieving data includes the step of retrieving the data from the forwarding descriptor from the output portion of the queue structure.

4. The method of claim 3, wherein the step of comparing includes the steps:

comparing the content of a unicopy field of the input data with the content of a unicopy field of the retrieved data;

comparing the content of a virtual LAN field of the input data with the content of a virtual LAN field of the retrieved data;

comparing the content of an opcode field of the input data with the content of an opcode field of the retrieved data; and

comparing the content of a frame pointer field of the input data with the content of a frame pointer field of the of the retrieved data.

5. The method of claim 1, wherein the step of inputting data includes the step of inputting data from prescribed fields of a forwarding descriptor onto a port vector index bus, the data being input from a port vector FIFO that queues forwarding descriptors received from a processor interface and an internal rules checker.

6. The method of claim 1, wherein the step of transferring the data includes the step of transferring the data to an output pointer bus of the output portion of the queue structure.

7. The method of claim 6, wherein the step of retrieving data includes the step of retrieving data from the output pointer bus of the output portion of the queue using a dequeuing logic.

8. The method of claim 7, further comprising the steps:

disabling the dequeuing logic; and

enabling a diagnostic register for retrieving data from the output portion of the queue structure.

9. Apparatus for testing the functionality of a queue structure that queues entries, said apparatus comprising:

an input circuit for inputting data into an input portion of the queue structure;

a data transfer circuit for transferring data from said input portion to an output portion of said queue structure;

an output circuit for retrieving data from the output portion of said queue structure; and

a comparison logic circuit for comparing the retrieved data with the input data to determine the integrity thereof by verifying that the input data has not been altered by said data transfer circuit;

whereby the integrity of said data indicates the functionality of said queue structure.

10. The apparatus of claim 9, wherein said comparison logic circuit includes circuitry for inputting the retrieved data back into the input portion of said queue structure.

11. The apparatus of claim 9, wherein said output circuit includes:

an output pointer bus for receiving the data from said transfer circuit; and

a dequeuing logic for retrieving data from the said output pointer bus and maintaining the ordering of entries retrieved from said queue structure.

12. The apparatus of claim 9, wherein the data input by said input circuit includes data from prescribed fields of a forwarding descriptor, said prescribed fields including:

a unicopy field that indicates whether a data frame will be copied only one port;

a virtual LAN field that stores an identifier for a virtual local area network;

an Opcode field that stores control information for the data frame; and

a frame pointer field that points to the location of the data frame in an external memory.

13. The apparatus of claim 12, wherein said comparison logic circuit includes circuitry for respectively comparing the unicopy, virtual LAN, opcode, and frame pointer fields of said input data and said retrieved data.

14. The apparatus of claim 12, wherein said input circuit includes a port vector index bus for receiving said data.

15. The apparatus of claim 14, further comprising a port vector FIFO for queuing forwarding descriptors received from a processor interface and an internal rules checker, and inputting data from said prescribed fields onto said port vector index bus.

16. The apparatus of claim 9, wherein said comparison logic circuit further comprises:

an interrupt circuit for disabling said dequeuing logic while testing data in said queue structure; and

a diagnostic register for retrieving data from said output circuit;

whereby retrieved data stored in said diagnostic register may be compared with data input to the queue structure to determine the integrity of said queue structure.