Parameter adjustment in a MOS integrated circuit

• US 6,346,427 B1
• Filed: 08/18/1999
• Issued: 02/12/2002
• Est. Priority Date: 08/18/1999
• Status: Expired due to Term

• Current Assignee: Aeroflex Colorado Springs Incorporated (Cobham PLC)
• Original Assignee: UTMC Microelectronic Systems, Inc. (Cobham PLC)
• Inventors: Gardner, Harry N., Lahey, Michael D., Pohlenz, Peter M., Patton, Stacia L., Harris, Debra S.
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Thompson, Craig
• Application Number:
  US09/376,246
• Time in Patent Office: 909 Days
• Field of Search: 438/10, 438/5-13, 438/14-18, 438/800, 352/40, 364/512
• US Class Current: 438/10
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out

Abstract

A method of manufacturing an integrated circuit including adjusting a parameter of the operation of the integrated circuit, such as power dissipation, after prototype testing by changing only one mask. If prototype testing indicates that the performance specification for power dissipation, for example, is not met, the power dissipation can be adjusted by changing the size of the active areas to change the channel width of the gates of the circuit, by changing the size of the patterns of the active area masks. To decrease power dissipation, the size of the active area is decreased. Only the active mask need be changed. Preferably, the active area around the original contacts are maintained so that the positions of the contacts need not be changed. Consequently, the mask for defining the position of the contacts and the masks for defining the metallization layers need not be changed. To increase power dissipation, the size of the active areas is increased. The values of other parameters may be changed, as well.

Claims

1. A method of manufacturing an integrated circuit to meet performance specifications for power dissipation, comprising:

a) fabricating at least one first prototype integrated circuit with a set of masks including a first mask for defining at least one active area of the integrated circuit;

b) testing the at least one prototype integrated circuit to determine whether performance specifications are met;

c) determining the size of the at least one active area required to meet the performance specifications based on the test results, if the performance specifications are not met;

d) creating a second mask for defining the at least one active area having the determined size;

e) replacing the first mask by the second mask to create a second set of masks;

f) fabricating at least one second prototype integrated circuit with the second set of masks;

g) testing the at least one second prototype integrated circuit to determine whether performance specifications are met; and

h) proceeding with manufacture of the integrated circuit with the second set of masks if the performance specifications are met.

2. The method of claim 1, wherein, if the performance specification are not met, the method further comprises repeating steps c) through g) to create one or more subsequent masks for defining the at least one active area for fabrication of at least one subsequent prototype integrated circuit, until the performance specifications are met.

3. The method of claim 1, wherein step g) comprises testing the at least one second prototype integrated circuit to determine whether the power dissipation performance specifications are met.

4. The method of claim 1, comprising growing field oxide in at least one region of the substrate of the second prototype integrated circuit which was part of the at least one active area in the first integrated circuit.

5. The method of claim 1, wherein step c) comprises determining the gate width required for providing the power dissipation of the performance specifications and determining the size of the active area required to provide said gate width.

6. The method of claim 5, comprising reducing the size of the active area to reduce the gate width and decrease power dissipation.

7. The method of claim 1, comprising creating a second mask for defining the at least one active area, the second mask having a portion for defining a portion of the active area at the original positions of the contacts to the active area.

8. The method of claim 7, comprising fabricating at least one first prototype integrated circuit with a set of masks including a mask for defining at least one contact to the active area midway between adjacent gates.

9. A method of reconfiguring parameters of transistors in a metal oxide semiconductor integrated circuit to meet performance specifications after testing of a prototype of the integrated circuit fabricated by a set of masks, comprising:

determining a size of at least one active area of the integrated circuit required to meet the performance specifications, based on the testing of the prototype integrated circuit, if the testing indicates that a parameter of the integrated circuit does not meet the performance specifications; and

creating a new mask for defining the at least one active area based on the determining step.

10. The method of claim 9, wherein the set of masks includes an active area mask for defining the at least one active area, the method further comprising replacing the active area mask of the set of masks by the new mask.

11. The method of claim 10, further comprising fabricating at least one second prototype integrated circuit with the set of masks including the new mask and testing the at least one second prototype integrated circuit.

12. The method of claim 10, comprising determining the gate width for providing the power dissipation of the performance specifications and determining the size of the at least one active area to define the gate width.

13. The method of claim 12, comprising reducing the size of the active area to reduce the gate width and decrease power dissipation.

14. The method of claim 10, comprising creating a new mask for defining the at least one active area, the new mask having a portion for defining a portion of the active area at the original position of the contacts to the active area at the position of contacts to the active area.

15. The method of claim 14, comprising fabricating at last one first prototype integrated circuit with a set of masks including a mask for defining at least one contact to the active area midway between adjacent gates.

16. A method of adjusting parameters of transistors in a metal oxide semiconductor logic circuit after prototype testing, comprising:

fabricating at least one prototype logic circuit with a set of custom masks; and

adjusting the parameters of the logic circuit by changing the configuration of only one layer of the transistor of the logic circuit.

17. The method of claim 16, comprising adjusting the power dissipation of the logic circuit.

18. The method of claim 17, comprising adjusting the power dissipation by changing the size of the active area.

19. The method of claim 18, wherein the creating step further comprises changing the shape of the changed layer.

20. The method of claim 16, further comprising testing the prototype logic circuit to verify the operation of the prototype logic circuit.

21. The method of claim 16, wherein the adjusting step comprises creating a new mask for defining the configuration of the changed layer.

22. The method of claim 21, further comprising replacing the original mask for defining the configuration of the changed layer by the new mask in the set of custom masks and fabricating another logic circuit with the set of masks including the new mask.

23. The method of claim 16, comprising creating a second mask for defining the at least one active area, the new mask having a portion for defining a portion of the active area at the original position of the contacts to the active area.

24. The method of claim 23, comprising fabricating at least one first prototype integrated circuit with a set of masks including a mask for defining at least one contact to the active area midway between adjacent gates.

25. A method of reconfiguring parameters of transistors in a metal oxide semiconductor integrated circuit after prototype testing to decrease power dissipation to meet performance specifications, the integrated circuit having been made in a fabrication process using a set of masks including a first mask for defining the active areas of the integrated circuit, comprising:

determining the configuration of the active areas of the integrated circuit to decrease gate widths to decrease the power dissipation, based on the test results; and

creating a new mask for defining the active areas, the new mask having a portion for defining a portion of the active area at the original position of the contacts to the active area.

26. The method of claim 25, further comprising:

replacing the first mask by the new mask in the set of masks, the other masks remaining the same; and

fabricating a second prototype integrated circuit with the set of masks including the new mask.

27. The method of claim 25, comprising fabricating at least one first prototype integrated circuit with a set of masks including a mask for defining at least one contact to the active area midway between adjacent gates.