Method and apparatus for minimizing semiconductor wafer arcing during semiconductor wafer processing

• US 6,346,428 B1
• Filed: 08/17/1998
• Issued: 02/12/2002
• Est. Priority Date: 08/17/1998
• Status: Expired due to Term

• Current Assignee: OEM Group, LLC
• Original Assignee: Tegal Corp. (Rennova Health, Inc.)
• Inventors: Meyer, John A., Jerde, Leslie G., Athavale, Satish D.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Luk, Olivia T
• Application Number:
  US09/135,210
• Time in Patent Office: 1,275 Days
• Field of Search: 438/14, 438/17, 361/234
• US Class Current: 438/14
• CPC Class Codes: H01L 21/6833 Details of electrostatic chucks

Abstract

A method and apparatus for minimizing or eliminating arcing or dielectric breakdown across a wafer during a semiconductor wafer processing step includes controlling the voltage across the wafer so that arcing and/or dielectric breakdown does not occur. Using an electrostatic clamp of the invention and by controlling the specific clamp voltage to within a suitable range of values, the voltage across a wafer is kept below a threshold and thus, arcing and/or dielectric breakdown is reduced or eliminated.

Claims

1. A method for reducing arcing across a workpiece in a plasma reactor including the steps of:

placing a workpiece into a reactor onto a monopolar chuck with a single electrostatic clamp electrode, the workpiece having a first side facing away from the monopolar chuck and a second side facing the monopolar chuck;

generating a plasma in the reactor, the plasma contacting the first side of the workpiece; and

controlling a voltage potential between the first side and second side of the workpiece by controlling a voltage applied to the single electrostatic clamp electrode of the chuck in order to minimize arcing between the first side and the second side of the workpiece.

2. The method of claim 1 wherein:

said controlling step occurs prior to the step of generating a plasma.

3. The method of claim 1 wherein:

said controlling step occurs at anytime when there is a plasma in the reactor.

4. The method of claim 1 including the steps of:

creating a voltage, V_dc, at the first side of the workpiece in contact with the plasma;

creating a voltage, V_ESC, at the second side of the workpiece in contact with the chuck; and

the controlling step includes controlling the difference between V_dc and V_ESC in order to minimize arcing.

5. The method of claim 4 wherein:

the controlling step includes minimizing the difference between V_dc and V_ESC.

11. The method of claim 1 wherein:

the step of generating a plasma includes applying one of a high frequency power supply and a low frequency power supply to the chuck.

12. The method of claim 1 wherein:

the step of generating a plasma includes applying both a high frequency power supply and a low frequency power supply to the chuck.

15. The method of claim 1 wherein:

said controlling step occurs during at least one of prior to a step of etching a workpiece, and during a step of etching a workpiece.

17. The method of claim 1 wherein:

said workpiece includes a layer of a high dielectric constant material.

18. The method of claim 1 wherein:

said workpiece includes a layer of a ferroelectric material.

21. The method of claim 1 including:

said generating step including (a) generating a plasma in a tri-electrode reactor with an upper and a lower electrode and a side electrode, and wherein said lower electrode is associated with the chuck, and (b) applying at least one of a high frequency power supply and a low frequency power supply to the lower electrode.

22. The method of claim 21 wherein:

said generating step includes applying both a high frequency power supply and a low frequency power supply to the lower electrode.

23. The method of claim 21 including the steps of:

grounding the upper electrode, and either grounding the side electrode, or allowing the side electrode to establish a floating potential.

6. A method for reducing arcing across a semiconductor wafer in a plasma reactor including the steps of:

placing a semiconductor wafer into a reactor onto a monopolar electrostatic chuck with a single electrostatic clamp electrode;

generating a plasma in the reactor; and

controlling a voltage applied by the single electrostatic clamp electrode of the electrostatic chuck to the wafer in order to minimize arcing between a first surface of the workpiece in contact with the plasma and a second surface of the workpiece in contact with the monopolar chuck.

7. The method of claim 6 wherein:

said controlling step occurs prior to the step of generating a plasma.

8. The method of claim 6 wherein:

said controlling step occurs at anytime when there is a plasma in the reactor.

9. The method of claim 6 including the steps of:

creating a voltage, V_dc, at a first surface of the wafer in contact with the plasma;

the controlling step includes creating a voltage, V_ESC, at a lower surface of the wafer in contact with the chuck; and

the controlling step further includes controlling the difference between V_dc and V_ESC in order to minimize arcing between the first surface and the second surface.

10. The method of claim 9 wherein:

the controlling step includes minimizing the difference between V_dc and V_ESC.

13. The method of claim 6 wherein:

the step of generating a plasma includes applying one of a high frequency power supply and a low frequency power supply to the chuck.

14. The method of claim 6 wherein:

the step of generating a plasma includes applying both a high frequency power supply and a low frequency power supply to the chuck.

16. The method of claim 6 wherein;

said controlling step occurs during at least one of prior to a step of etching a wafer, and during a step of etching a wafer.

19. The method of claim 6 wherein:

said wafer includes a layer of a high dielectric constant material.

20. The method of claim 6 wherein:

said wafer includes a layer of a ferroelectric material.

24. The method of claim 6 including:

said generating step including (a) generating a plasma in a tri-electrode reactor with an upper and a lower electrode and a side electrode, and wherein said lower electrode is associated with the chuck, and (b) applying at least one of a high frequency power supply and a low frequency power supply to the lower electrode.

25. The method of claim 24 wherein:

said generating step includes applying both a high frequency power supply and a low frequency power supply to the lower electrode.

26. The method of claim 25 including the steps of:

grounding the upper electrode, and either grounding the side electrode, or allowing the side electrode to establish a floating potential.