Method of manufacturing a semiconductor device

• US 6,346,438 B1
• Filed: 06/29/1998
• Issued: 02/12/2002
• Est. Priority Date: 06/30/1997
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Suguro, Kyoichi, Yagishita, Atsushi, Matsuo, Kouji, Akasaka, Yasushi, Tsunashima, Yoshitaka
• Primary Examiner(s): Wilczewski, Mary
• Application Number:
  US09/105,960
• Time in Patent Office: 1,324 Days
• Field of Search: 438/259, 438/270, 438/589, 438/296, 438/585, 438/586, 438/595, 438/197, 438/211, 438/272, 438/279, 438/283, 438/213, 438/218, 438/219, 438/221, 438/225, 438/294, 438/295, 438/297, 438/300, 438/926
• US Class Current: 438/197
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: Y10S 438/926 Dummy metallization

Abstract

A method of manufacturing a semiconductor device according to this invention is characterized by including the steps of a) forming, on one major surface of a substrate, a gate structure constituted by either one of a dummy gate electrode and a gate electrode having an insulating film at least on bottom surface, and a device isolation insulating film so as to form a first groove divided by the dummy gate electrode or the gate electrode, to position the dummy gate electrode or the gate electrode in the first groove, and to form the gate structure to have an upper surface level not higher than an upper level of the device isolation insulating film, and b) forming source and drain electrodes in the first groove.

Claims

1. A method of manufacturing a semiconductor device, comprising:

a) forming, on one major surface of a substrate,

a gate structure selected from the group consisting of

a first gate structure comprising a dummy gate wiring layer and a dummy gate electrode, and

a second gate structure comprising a gate wiring layer and a gate electrode, each of the gate wiring layer and the gate electrode being provided with an insulating film at least on a bottom surface thereof, and

a device isolation insulating film having a first groove, such that said dummy gate electrode or said gate electrode divides said first groove, and such that an upper surface level of said gate structure is not higher than an upper level of said device isolation insulating film; and

b) forming source and drain electrodes in the first groove by use of film forming and flattening,

wherein said dummy gate wiring layer or said gate wiring layer is formed on the device isolation insulating film, connected to said dummy gate electrode or said gate electrode, and crossing said first groove.

2. A method according to claim 1, further comprising respectively forming a source diffusion layer and drain diffusion layer in a surface region of said substrate corresponding to the first groove before the formation of said source and drain electrodes.

3. A method according to claim 1, wherein the formation of said source and drain electrodes comprises:

forming, on one entire major surface of said substrate, a first thin film made of either one of a material constituting said source and drain electrodes and a material used to form said source and drain electrodes; and

removing a portion of said first thin film located outside the first groove by using CMP.

4. A method according to claim 1, wherein said gate structure is the first gate structure, and

the method further comprises:

removing said first gate structure to form a second groove after the formation of said source and drain electrodes; and

forming an insulating film, a gate electrode, and a gate wiring layer in the second groove so that said gate electrode divides the gate wiring layer and positions between said source electrode and said drain electrode, and so that said insulating film is interposed between said gate wiring layer and an inner wall of the second groove.

5. A method according to claim 4, wherein said gate electrode and said gate wiring layer are simultaneously formed in one piece by:

forming a second thin film made of either one of a material constituting said gate wiring layer and material used to form said gate wiring layer, on one entire major surface of said substrate; and

removing a portion of said second thin film located outside the second groove by using CMP.

6. A method according to claim 4, further comprising, before the formation of said insulating film and said gate wiring layer:

doping, with a conductive impurity, a surface region of said substrate corresponding to the second groove; and

forming a semiconductor film on a bottom surface of the second groove by using epitaxial growth.

7. A method according to claim 1, wherein the formation of said gate structure and said device isolation insulating film comprises:

forming said device isolation insulating film on one major surface of said substrate;

forming a third groove in said device isolation insulating film;

forming, on one entire major surface of said substrate, a third thin film made of a material constituting said gate structure;

removing a portion of said third thin film located outside the third groove by using CMP; and

forming the first groove, at least a part of the sidewall of which is constituted by said device isolation insulating film, so as to cross the gate structure.

8. A method according to claim 1, wherein said source and drain electrodes are made of a metal.

9. A method according to claim 1, wherein said gate structure is the second gate structure, and said gate electrode and said gate wiring layer are made of a metal.

10. A method of manufacturing a semiconductor device, comprising:

a) forming, on one major surface of a substrate,

a gate structure comprising either one of a dummy gate electrode and a gate electrode which is provided with an insulating film at least on a bottom surface thereof, and

a device isolation insulating film having a first groove, such that said dummy gate electrode or said gate electrode divides said first groove, and such that an upper surface level of said gate structure is not higher than an upper level of said device isolation insulating film; and

b) forming source and drain electrodes in the first groove by use of film forming and flattening,

wherein the formation of said gate structure and said device isolation insulating film comprises forming a dummy wiring layer which is positioned above part of said device isolation insulating film, and said gate structure, and has an upper surface level higher than the upper surface level of said device isolation insulating film.

11. A method according to claim 10, further comprising, before the formation of said source and drain electrodes:

forming a fourth thin film on one entire major surface of said substate;

polishing said fourth thin film and exposing an upper surface of said dummy wiring layer; and

removing said dummy wiring layer to form a fourth groove in said fourth thin film.

12. A method according to claim 11, further comprises removing at least a part of an exposed portion of said device isolation insulating film in the fourth groove to form an eighth groove in a bottom of said fourth groove, between the formation of the fourth groove and the formation of said source and drain electrodes.

13. A method according to claim 11, wherein said gate structure is the dummy gate electrode, and

the method further comprises, between the formation of said fourth groove and the formation of said source and drain electrodes,

removing said dummy gate electrode to form a seventh groove in a bottom of said fourth groove;

and

forming a gate electrode in the fourth groove.

14. A method according to claim 13, further comprising, after the formation of said device isolation insulating film and said gate structure:

removing a portion of said device isolation insulating film to form a fifth groove; and

forming, in the fifth groove, a connection wiring layer connected to at least one of said source electrode, said drain electrode, and said gate wiring layer,

wherein the formation of said gate wiring layer and the formation of said connection wiring layer are performed simultaneously.

15. A method according to claim 11, wherein said fourth thin film is made of either one of a material constituting said source and drain electrodes and material used to form said source and drain electrodes.

16. A method according to claim 11, further comprising removing said fourth thin film before the formation of said source and drain electrodes.

17. A method according to claim 11, further comprising, after the formation of said device isolation insulating film and said gate structure:

removing a portion of said device isolation insulating film to form a fifth groove; and

forming, in the fifth groove, a connection wiring layer connected to at least one of said source electrode, said drain electrode, and said gate wiring layer.

18. A method according to claim 17, wherein the formation of said connection wiring layer and the formation of said source and drain electrodes are performed simultaneously.

19. A method according to claim 10, further comprising respectively forming a source diffusion layer and a drain diffusion layer in a surface region of said substrate corresponding to the first groove before the formation of said source and drain electrodes.

20. A method according to claim 10, wherein the formation of said source and drain electrodes comprises:

forming, on one entire major surface of said substrate, a first thin film made of either one of a material constituting said source and drain electrodes and a material used to form said source and drain electrodes; and

removing a portion of said first thin film located outside the first groove by using CMP.

21. A method according to claim 10, wherein said source and drain electrodes are made of a metal.

22. A method according to claim 10, wherein said gate structure comprises said gate electrode, and said gate electrode and said gate wiring layer are made of a metal.

23. A method of manufacturing a semiconductor device, comprising:

a) forming, on one major surface of a substrate,

a gate structure comprising either one of a dummy gate electrode and a gate electrode which is provided with an insulating film at least on a bottom surface thereof, and

a device isolation insulating film having a first groove, such that said dummy gate electrode or said gate electrode divides said first groove, and such that an upper surface level of said gate structure is not higher than an upper level of said device isolation insulating film;

b) forming a semiconductor film using epitaxial growth on a bottom surface of the first groove;

c) respectively forming source and drain diffusion layers in said semiconductor film groove;

d) forming source and drain electrodes in the first groove by use of film forming and flattening after the formation of the source and drain diffusion layers.

24. A method according to claim 23, further comprising respectively forming a source diffusion layer and drain diffusion layer in a surface region of said substrate corresponding to the first groove before the formation of said source and drain electrodes.

25. A method according to claim 23, wherein the formation of said source and drain electrodes comprises:

forming, on one entire major surface of said substrate, a first thin film made of either one of a material constituting said source and drain electrodes and a material used to form said source and drain electrodes; and

removing a portion of said first thin film located outside the first groove by using CMP.

26. A method according to claim 23, wherein said source and drain electrodes are made of a metal.

27. A method according to claim 23, wherein said gate structure comprises said gate electrode, and said gate electrode and said gate wiring layer are made of a metal.

28. A method of manufacturing a semiconductor device, comprising:

a) forming, on one major surface of a substrate,

a gate structure comprising either one of a dummy gate electrode and a gate electrode which is provided with an insulating film at least on a bottom surface thereof, and

a device isolation insulating film having a first groove, such that said dummy gate electrode or said gate electrode divides said first groove, and such that an upper surface level of said gate structure is not higher than an upper level of said device isolation insulating film; and

b) forming source and drain electrodes in the first groove by use of film forming and flattening, wherein the formation of said gate structure and said device isolation insulating film comprises;

forming, on one entire major surface of said substrate, a third thin film made of a material constituting said dummy gate wiring layer;

forming a second forward-tapered groove in said third thin film;

forming said device isolation insulating film an one major surface of said substrate;

removing a portion of said device isolation insulating film located outside the second groove by using CMP; and

anisotropically etching said third thin film to simultaneously form said gate structure and first groove, and a sidewall on a side surface of said device isolation insulating film.

29. A method according to claim 28, further comprising respectively forming a source diffusion layer and drain diffusion layer in a surface region of said substrate corresponding to the first groove before the formation of said source and drain electrodes.

30. A method according to claim 28, wherein the formation of said source and drain electrodes comprises:

forming, on one entire major surface of said substrate, a first thin film made of either one of a material constituting said source and drain electrodes and a material used to form said source and drain electrodes; and

removing a portion of said first thin film located outside the first groove by using chemical mechanical polishing.

31. A method according to claim 28, wherein said source and drain electrodes are made of a metal.

32. A method according to claim 28, wherein said gate structure comprises said gate electrode, and said gate electrode and said gate wiring layer are made of a metal.