Manufacturing method of semiconductor device

• US 6,346,464 B1
• Filed: 06/27/2000
• Issued: 02/12/2002
• Est. Priority Date: 06/28/1999
• Status: Expired

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tsunoda, Tetsujiro, Takeda, Toru
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Anya, Igwe U.
• Application Number:
  US09/604,100
• Time in Patent Office: 595 Days
• Field of Search: 438/514, 438/268, 438/184, 438/270, 438/299, 438/302, 438/303, 438/305, 438/348, 438/366, 438/639, 438/210, 438/217, 438/228, 438/451
• US Class Current: 438/514
• CPC Class Codes: H01L 21/261 to produce a nuclear reaction transmuting chemical elements
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A method of manufacturing a low power dissipation semiconductor power device is provided which is easy to perform and suitable for mass production. When a first and second conductivity-type regions are formed on a semiconductor substrate which is selectively irradiated by impurity ions, an excellent super junction is formed by controlling the ion acceleration energy and the width of each irradiated region so that the first and second conductivity-type regions may have a uniform impurity distribution and a uniform width along the direction of irradiation. Another method of manufacturing a low power dissipation semiconductor power device having an excellent super junction is provided which selectively irradiates a collimated neutron beam onto a P⁺ silicon ingot and forms an N⁺ region that has a uniform impurity distribution and a uniform width along the direction of irradiation in the P⁺ silicon ingot.

Claims

1. A semiconductor device manufacturing method of forming a second conductivity-type region by irradiating impurity ions onto a first conductivity-type semiconductor substrate;

wherein the impurity ion irradiated region is restricted by a shield mask intercepting said impurity ions and the impurity ion acceleration energy is controlled to provide a uniform impurity distribution in the direction of irradiation in said second conductivity-type region.

2. A semiconductor device manufacturing method of forming at least one of a first and second conductivity-type regions in a semiconductor substrate by selectively irradiating impurity ions onto said semiconductor substrate;

wherein the impurity distributions in said first and second conductivity-type regions are uniform in the direction of irradiation, and the impurity ion acceleration energy and the area of each region irradiated by said impurity ions are controlled so that the cross-sectional shape and cross-section area of said first and second conductivity-type regions on planes perpendicular to the direction of irradiation may be uniform in the direction of irradiation.

3. The semiconductor device manufacturing method according to claim 2, wherein the control of the area of said irradiated region comprises the steps of forming an ion beam made of impurity ions and sweeping the ion beam in the vertical and horizontal directions on the irradiated region, and the acceleration energy and the area of the irradiated region are controlled by changing the area of said irradiated region according to changes in said acceleration energy.

4. The semiconductor device manufacturing method according to claim 3, wherein said impurity ion beam is electrically swept on the irradiated region.

5. The semiconductor device manufacturing method according to claim 3, wherein said impurity ion beam is magnetically swept on the irradiated region.

6. The semiconductor device manufacturing method according to claim 3, wherein said impurity ion beam is swept on the irradiated region by moving the semiconductor substrate.

7. The semiconductor device manufacturing method according to claim 3, wherein the acceleration energy and the area of the irradiated region are controlled by decreasing the area of the irradiated region according to increase in the acceleration energy.

8. The semiconductor device manufacturing method according to claim 3, wherein the acceleration energy and the area of the irradiated region are controlled by increasing the area of the irradiated region according to decrease in the acceleration energy.

9. The semiconductor device manufacturing method according to claim 2, wherein the area of the irradiated region is restricted by a shield mask intercepting said impurity ions, and the acceleration energy and the area of the irradiated region are controlled by changing the area of each opening of said shield mask intercepting impurity ions according to changes in the acceleration energy.

10. The semiconductor device manufacturing method according to claim 9, wherein the acceleration energy and the area of the irradiated region are controlled by decreasing the area of each opening of said shield mask intercepting impurity ions according to increase in the acceleration energy.

11. The semiconductor device manufacturing method according to claim 9, wherein the acceleration energy and the area of the irradiated region are controlled by increasing the area of each opening of said shield mask intercepting impurity ions according to decrease in the acceleration energy.

12. A semiconductor device manufacturing method of forming a first conductivity-type region and a second conductivity-type region on a semiconductor substrate by irradiating impurity ions onto said semiconductor substrate;

wherein the regions irradiated by impurity ions are restricted by impurity ion intercepting shield masks which are in an inverted imaging relation to each other so that the cross-sectional shape and the cross-section area of the first and second conductivity-type regions on planes perpendicular to the direction of irradiation may be uniform along the direction of irradiation, and the impurity ion acceleration energy is controlled to make the impurity ion distributions in the first and second conductivity-type regions uniform along the direction of irradiation.

13. The semiconductor device manufacturing method according to claim 12, wherein said impurity ion intercepting shield masks which are in an inverted imaging relation to each other are formed by printing the same mask patterns on the semiconductor substrate by the use of a positive resist and a negative resist.

14. A semiconductor device manufacturing method of forming an N⁺ region by irradiating a neutron beam onto a semiconductor ingot having a P⁺ region;

wherein the incident direction of said neutron beam is collimated to make the cross-sectional shape and the cross-section area of said N⁺ region on planes perpendicular to the direction of irradiation uniform along the direction of irradiation, and the impurity distribution in said N⁺ region is controlled to be uniform along the direction of irradiation.

15. The semiconductor device manufacturing method according to claim 14, wherein the semiconductor having the P⁺ region is an P⁺ type semiconductor ingot and the incident direction of said neutron beam is parallel to the growth axis of said P⁺ type semiconductor ingot.

16. The semiconductor device manufacturing method according to claim 14, wherein said semiconductor ingot is made of silicon.

17. The semiconductor device manufacturing method according to claim 14, wherein said semiconductor ingot is made of germanium.

18. The semiconductor device manufacturing method according to claim 14, wherein said semiconductor ingot is made of silicon carbide.