Semiconductor device and a process for forming the semiconductor device

• US 6,346,469 B1
• Filed: 01/03/2000
• Issued: 02/12/2002
• Est. Priority Date: 01/03/2000
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Greer, Stuart E.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Lee, Calvin
• Application Number:
  US09/476,810
• Time in Patent Office: 771 Days
• Field of Search: 257/737, 257/738, 257/743, 257/772, 257/751, 438/613, 438/614, 438/623, 438/625, 438/632, 438/615, 438/616, 438/15, 438/17, 438/250
• US Class Current: 438/614
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/11901 with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/13019 at the bonding interface of the bump connector, i.e. on the surface of the bump connector
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/81024 Applying flux to the bonding area
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81203 Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides

Abstract

Conductive bumps (32) are formed to overlie a semiconductor die (11). The conductive bumps (32) typically have reduced levels of lead, flow at a temperature no greater than 260° C., and have reduced problems associated with alpha particles. In one embodiment, the conductive bump (32) includes a mostly tin (20) with a relatively thin layer of lead (30). The lead (30) and a portion of the tin (20) interact to form a relatively low melting solder close to the eutectic point for lead and tin. Most of the tin (20) remains unreacted and can form a stand off between the semiconductor die (11) and the packaging substrate (42). Other metals and impurities can be used to improve the mechanical or electrical properties of the conductive bumps (32).

Claims

1. A process for forming a semiconductor die comprising:

forming a die interconnect pad over a semiconductor device substrate; and

forming a conductive bump over and electrically connected to the die interconnect pad, wherein;

the conductive bump includes a first metallic layer and a second metallic layer, wherein;

the first metallic portion lies closer to the semiconductor die compared to the second metallic portion, is a main portion of the conductive bump, and does not substantially include lead; and

the second metallic portion is a farthest metallic portion of the conductive bump with respect to the semiconductor die, and wherein the second metallic portion includes lead.

2. The process of claim 1, wherein the conductive bump is formed using electroplating.

3. The process of claim 1, wherein the conductive bump is formed using evaporation.

4. The process of claim 1, wherein the conductive bump is formed using physical vapor deposition.

5. The process of claim 1, further comprising forming an underbump layer over the die interconnect pad and before forming the conductive bump.

6. The process of claim 1, wherein at least one of the first and second metallic layers includes an alloy during its formation.

7. A process for forming a semiconductor die comprising:

placing a semiconductor die and a substrate in contact with each other, wherein;

the semiconductor includes a die interconnect pad and a conductive bump including a first metallic layer and a second metallic layer;

the first metallic layer lies closer to the semiconductor die compared to the second metallic layer, is a main portion of the conductive bump and does not substantially include lead; and

the second metallic portion is a farthest metallic portion of the conductive bump with respect to the semiconductor die and includes lead; and

flowing a portion, but not all, of the conductive bump.

8. The process of claim 7, wherein flowing is performed at a temperature lower than a melting point of the first metallic layer.

9. The process of claim 7, wherein the flowing is performed at a temperature no greater than approximately 260°

C.

10. The process of claim 7, wherein the first metallic layer has a melting point of at least approximately 201°

C.

11. The process of claim 7, wherein the substrate includes an organic portion.

12. The process of claim 7, wherein the first metallic layer is thicker than the second metallic layer, and wherein the second metallic layer is a farthest metallic layer of the conductive bump with respect to the semiconductor die, and wherein the second metallic layer includes lead.

13. A process for forming a semiconductor die comprising:

forming a die interconnect pad over a semiconductor device substrate; and

forming a conductive bump over and electrically connected to the die interconnect pad, wherein;

the conductive bump includes a first metallic layer and a second metallic layer, wherein;

the first metallic portion lies closer to the semiconductor die compared to the second metallic portion;

the first metallic portion and the second metallic portion are of different materials;

the second metallic portion contains lead; and

the conductive bump includes less than approximately 25 weight percent lead .

14. The process of claim 13, wherein the conductive bump is formed using electroplating.

15. The process of claim 13, wherein the conductive bump is formed using evaporation.

16. The process of claim 13, wherein the conductive bump is formed using physical vapor deposition.

17. A process for forming a semiconductor die comprising:

placing a semiconductor die and a substrate in contact with each other, wherein;

the semiconductor includes a die interconnect pad and a conductive bump including a first metallic layer and a second metallic layer, wherein;

the first metallic portion lies closer to the semiconductor die compared to the second metallic portion;

the first metallic portion and the second metallic portion are of different materials;

the second metallic portion contains lead; and

the conductive bump includes less than approximately 25 weight percent lead; and

flowing a portion, but not all, of the conductive bump.

18. The process of claim 17, wherein flowing is performed at a temperature lower than a melting point of the first metallic layer.

19. The process of claim 17, wherein the substrate includes an organic portion.

20. The process of claim 17, wherein the first metallic layer is thicker than the second metallic layer.