Semiconductor integrated circuit having diagnosis function

• US 6,346,822 B2
• Filed: 12/13/2000
• Issued: 02/12/2002
• Est. Priority Date: 12/14/1999
• Status: Expired due to Term

• Current Assignee: Socionext Inc.
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Nishikawa, Yoshikazu
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Chang, Daniel D.
• Application Number:
  US09/735,757
• Publication Number:
  US 20010004123A1
• Time in Patent Office: 426 Days
• Field of Search: 326/16, 326/46, 326/93, 714/728, 714/724, 714/726, 324/765, 324/76.82
• US Class Current: 326/16
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern
• CPC Class Codes: G01R 31/318566 Comparators; Diagnosing the device under test
• CPC Class Codes: H03K 3/84 Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators

Abstract

A semiconductor integrated circuit having a diagnosis function includes a scan chain arrangement block 2 in which a plurality of flip-flops are connected so that they can be shift-registered, and designed in a scan-path manner; a shift register 3 for storing required bits of a first random number pattern shifted by the block 2; another shift register 4 for storing required bits of a second random number pattern supplied to the block 2; and a comparator for comparing corresponding bits of the random number patterns stored in the shift registers 3 and 4 to detect whether all the bits of the random number patterns agree or disagree with each other, thereby verifying a normal operation of the block 2. In this configuration, the operating state of the semiconductor integrated circuit can be diagnosed with the number of connecting wires connected to it being minimized.

Claims

1. A semiconductor integrated circuit having a diagnosis function comprising:

a logic circuit to which a random number pattern is supplied, said logic circuit designed in a scan-path manner and having a plurality of flip-flops which can be shift-registered;

a first shift register for storing required bits of a first random number pattern shifted by said logic circuit;

a second shift register for storing required bits of a first random number pattern supplied to said logic circuit; and

means for comparing corresponding bits of the random number patterns stored in the first and the second shift register to detect whether all the bits of the first and second random number patterns agree or disagree with each other, thereby verifying a normal operation of said logic circuit.

2. A semiconductor integrated circuit having a diagnosis function according to claim 1 further comprising:

determination means which produces a success decision signal when the normal operation of said logic circuit is verified by said comparing means and produces an error decision signal when the normal operation of said logic circuit is not verified within a prescribed time by said comparing means.

3. A semiconductor integrated circuit having a diagnosis function according to claim 1 further comprising:

random number generating means for said random number pattern or pseudorandom number pattern, wherein the logic circuit is subjected to burn-in testing of applying suitable stress to said logic circuit, thereby verifying the normal operation of said logic circuit.

4. A semiconductor integrated circuit having a diagnosis function comprising:

a logic circuit to which a pseudorandom number pattern of a string of M bits touring at a period of (2^M−

1) and not having a repetition within the period is supplied, said logic circuit designed in a scan-path manner and having a plurality of flip-flops which can be shift-registered;

a shift register for storing required bits of a first random number pattern shifted by said logic circuit;

holding means for holding data for comparison composed of any string of bits of said pseudorandom number pattern; and

comparing means for comparing corresponding bits of the random number pattern stored in said shift register and data for comparison held in said holding means to detect whether all the bits of the random number patterns agree and/or disagree with each other, thereby verifying a normal operation of said logic circuit.

5. A semiconductor integrated circuit having a diagnosis function according to claim 4 comprising:

determination means which produces a success decision signal when the normal operation of said logic circuit is verified by said comparing means and produces an error decision signal when the normal operation of said logic circuit is not verified within a prescribed time by said comparing means.

6. A semiconductor integrated circuit having a diagnosis function according to claim 4 further comprising:

random number generating means for said random number pattern or pseudorandom number pattern, wherein the logic circuit is subjected to burn-in testing of applying suitable stress to said logic circuit, thereby verifying the normal operation of said logic circuit.