Dedicated function fabric for use in field programmable gate arrays

• US 6,346,824 B1
• Filed: 07/27/2000
• Issued: 02/12/2002
• Est. Priority Date: 04/09/1996
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: New, Bernard J.
• Primary Examiner(s): TAN, VIBOL
• Application Number:
  US09/627,247
• Time in Patent Office: 565 Days
• Field of Search: 326/38, 326/39, 326/40, 326/41
• US Class Current: 326/39
• CPC Class Codes: G06F 7/5324 partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

A programmable logic device, such as a field programmable gate array (FPGA) which includes an array of configurable logic elements (CLEs) and a corresponding array of dedicated function blocks. The CLEs can be operated as conventional configurable logic elements, completely disconnected from the array of function blocks. However, selected CLEs can also be coupled to selected function blocks, thereby creating a relatively high density circuit to implement the dedicated function. The function blocks can be selectively coupled to one another, such that the function blocks are connected to form a relatively large circuit. The desired input signals are routed into the function blocks from associated CLEs. Similarly, the resulting output signals are routed from the function blocks to associated CLEs. In this manner, the FPGA is capable of implementing a relatively large circuit having the dedicated function in an efficient manner.

Claims

1. A programmable logic device comprising:

an array of configurable logic elements (CLEs);

an array of dedicated function blocks; and

programmable interconnect resources for selectively coupling each of the dedicated function blocks to a corresponding one of the CLEs and to adjacent dedicated function blocks.

2. The programmable logic device of claim 1, further comprising programmable interconnect resources for selectively coupling the CLEs.

3. The programmable logic device of claim 1, wherein the programmable interconnect resources comprise a plurality of programmable multiplexers for selectively connecting or isolating the dedicated function blocks and the corresponding CLEs.

4. The programmable logic device of claim 1, wherein the programmable interconnect resources comprise a plurality of programmable multiplexers for selectively connecting or isolating adjacent dedicated function blocks.

5. The programmable logic device of claim 1, wherein each of the CLEs comprises:

a programmable function generator; and

a programmable carry logic circuit.

7. The programmable logic device of claim 1, wherein each of the CLEs comprises a programmable function generator and a register.

6. A method of operating a programmable logic device, the method comprising the steps of:

providing an array of configurable logic elements (CLEs) and an array of dedicated function blocks;

selectively coupling a first set of the dedicated function blocks to form a circuit;

coupling a first subset of dedicated function blocks within the first set of dedicated function blocks to a first subset of associated CLEs;

routing signals from the first subset of CLEs to the first subset of dedicated function blocks;

coupling a second subset of dedicated function blocks within the first set of dedicated function blocks to a second subset of associated CLEs; and

routing signals from second subset of dedicated function blocks to the second subset of CLEs.