Local memory unit system with global access for use on reconfigurable chips

• US 6,347,346 B1
• Filed: 06/30/1999
• Issued: 02/12/2002
• Est. Priority Date: 06/30/1999
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Chameleon Systems, Inc.
• Inventors: Taylor, Bradley L.
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): DU, THUAN N
• Application Number:
  US09/343,477
• Time in Patent Office: 958 Days
• Field of Search: 326/38, 326/40, 326/41, 710/22, 710/23, 710/52, 710/129, 711/170, 364/521, 365/189.01, 365/63, 365/230.03, 365/189.08, 365/230.06
• US Class Current: 710/23
• CPC Class Codes: H03K 19/1776 for memories

Abstract

A memory access system is described in which local memory units on a reconfigurable chip can be used in conjunction with the system memory. Data path units on the reconfigurable chip can cause data to be swapped in and out of the local memory units as a result of calculations within the reconfigurable fabric. Alternately, a cache-like system can be used so that the data can be read into the local memory unit from the system memory units automatically.

Claims

1. A reconfigurable chip comprising:

a number of data path units able to implement a number of functions, the data path units receiving input data and producing output data as determined by the implemented function;

a number of dedicated local memory units operably connected to data path units, the local memory units storing N elements by M bits, the local memory units including at least one global system port and at least one local port, the local port adapted for data path unit data transfers, at least one of the local memory units adapted to store data to be provided as input data to at least one of the data path units using the at least one local port; and

a global memory access means operably connected to the global system ports for interconnection to a system memory.

2. The reconfigurable chip of claim 1, wherein the data path units can initiate a data transfer between local memory units and a system memory.

3. The reconfigurable chip of claim 2, wherein the data path units use instructions and wherein

at least one of the instructions can initiate data transfer between local memory units and a system memory.

4. The reconfigurable chip of claim 1, wherein the system memory is external to the reconfigurable chip.

5. The reconfigurable chip of claim 1, wherein the global memory access means includes a bus operably connected to the global system ports.

6. The reconfigurable chip of claim 5, wherein the global memory access means further includes a direct memory access (DMA) controller connected to the bus.

7. The reconfigurable chip of claim 1, wherein the local memory units are arranged with fixed memory addresses with respect to the global memory access means.

8. The reconfigurable chip of claim 1, wherein the data path units are operably connected to a request line to initiate a data transfer between local memory units and a system memory.

9. The reconfigurable chip of claim 8, wherein the request line is connected to a direct memory access (DMA) controller.

10. The reconfigurable chip of claim 1 wherein the local memory units further include a local read port and a local write port.

11. The reconfigurable chip of claim 1, further comprising reconfigurable connections on local bus lines between local memory units, the reconfigurable connections allowing the selective connection of local memory units.

12. The reconfigurable chip of claim 1, wherein the reconfigurable chip is arranged to implement a memory structure.

13. The reconfigurable chip of claim 12, wherein the reconfigurable chip is arranged to implement a first-in-first-out (FIFO) buffer.

14. The reconfigurable chip of claim 12, wherein the data is swapped between the local memory unit and the system memory unit to implement the memory structure.

15. The reconfigurable chip of claim 1, wherein the local memory units act as cache memory units for the system memory.

16. The reconfigurable chip of claim 15, wherein associated with the local memory units are automatic memory swapping units.

17. The reconfigurable chip of claim 15, wherein the automatic memory swapping units include a tag memory and comparator.

18. The reconfigurable chip of claim 15, wherein the system uses valid bits to indicate whether data in the local memory unit is valid.

19. The reconfigurable chip of claim 1, wherein the local memory units are read and write addressable by the data path units.

20. The reconfigurable chip of claim 1, further comprising reconfigurable connections on local bus lines between data path units and local memory units to operably connect the data path units and local memory units, the reconfigurable connections allowing addresses from one of the data path units to be sent to a single local memory unit or a group of local memory units.

21. The reconfigurable chip of claim 1, wherein the data path units and local memory units are arranged into slices.

22. The reconfigurable chip of claim 1, wherein the reconfigurable chip is arranged for reconfigurable computing.

23. A reconfigurable chip comprising:

a number of data path units able to implement a number functions, the data path units receiving input data and producing output data as determined by the implemented function; and

a number of dedicated local memory units operably connected to data path units, the local units storing N elements by M bits, the local memory units including at least one global system port and at least one local port, the local port adapted for data path units data transfers, wherein at least one of the data path unit can initiate a data transfer between at least one of the local memory units and a system memory, the data transfer using the global system port of the at least one of the local memory units.

24. The reconfigurable chip of claim 23, wherein the data path unit can initiate a block data transfer of multiple data elements between local memory units and a system memory.

25. The reconfigurable chip of claim 23, wherein the data path units are operably connected to a request line to initiate a data transfer between local memory units and a system memory.

26. The reconfigurable chip of claim 23, wherein the data path units use instructions and wherein at least one of the instructions can initiate data transfer between local memory units and a system memory.

27. The reconfigurable chip of claim 23, wherein determination of a data transfer is the result of calculation by one of the data path units.

28. The reconfigurable chip of claim 23, wherein the local address, system address, data transfer length indications are sent to a data memory access (DMA) unit from at least one data path unit to implement the data transfer.

29. The reconfigurable chip of claim 23, wherein the data transfer is from the system memory to a local memory unit.

30. The reconfigurable chip of claim 23, further comprising a global memory access means operably connected to the global system ports for interconnection to a system memory.

31. A method of implementing a memory structure on a reconfigurable chip, the reconfigurable chip including a number of dedicated local memory units, the method comprising:

implementing a memory structure on the reconfigurable chip, the memory structure including at least one of the local memory units, wherein the local memory units including at least one global system port;

operating the memory structure;

in response to the operating step, swapping data between the at least one of the local memory unit and a system memory.

32. The method of claim 31, wherein the swapping step is automatic.

33. The method of claim 31, wherein the swapping step uses a tag memory and comparator.

34. The method of claim 31, wherein the swapping step is initiated by a data path unit on the reconfigurable chip.

35. The method of claim 31, wherein some of the data of the implemented memory structure is stored in the local memory units and other data of the data of the implemented memory structure is stored in the system memory.

36. The method of claim 35, wherein the swapping step comprises moving data out of a local memory unit to the system memory when the local memory unit is full of data for the implemented memory structure.

37. The method of claim 35, wherein the swapping step comprises moving data from the system memory unit to a local memory unit the local memory unit is emptied of data for the implemented memory structure.

38. The method of claim 31, wherein the implemented memory structure is a first-in-first-out (FIFO) buffer.

39. The method of claim 31, wherein the implemented memory structure comprises tree data structure.

40. The method of claim 31, wherein the implemented memory structure comprises a table data structure.

41. A reconfigurable chip comprising:

a number of reconfigurable units able to implement a number of computational functions, the reconfigurable units receiving input data and producing output data as determined by the implemented function;

a number of dedicated local memory units operably connected to the reconfigurable units, the local memory units storing N elements by M bits, the local memory units including at least one global system port and at least one local port, the local port adapted for reconfigurable unit data transfers, at least one of the local memory units adapted to store data to be provided as input data to at least one of the reconfigurable units using the at least one local port; and

a global memory access means operably connected to the global system ports for interconnection to a system memory.

42. The reconfigurable chip of claim 41, wherein the reconfigurable units are data path unit.

43. (Amended) A reconfigurable chip comprising:

a number of reconfigurable units able to implement a number of computational functions, the reconfigurable units receiving input data and producing output data as determined by the implemented function; and

a number of dedicated local memory units operably connected to reconfigurable units, the local memory units storing N elements by M bits, the local memory units including at least one global system port and at least one local port, the local port adapted for reconfigurable unit data transfers, wherein at least one of the reconfigurable units can initiate a data transfer between at least one of the local memory units and a system memory, the data transfer using the global system port of the at least one of the local memory units.

44. The reconfigurable chip of claim 43, wherein the reconfigurable unit is a data path unit.