Multiprocessor control system, and a boot device and a boot control device used therein

• US 6,347,372 B1
• Filed: 03/18/1999
• Issued: 02/12/2002
• Est. Priority Date: 03/20/1998
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Chujo, Kaoru, Takashima, Tomonobu
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US09/271,332
• Time in Patent Office: 1,062 Days
• Field of Search: 713/2, 709/220, 709/222, 710/104
• US Class Current: 713/2
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 9/4405 Initialisation of multiprocessor systems

Abstract

A multiprocessor control system includes a plurality of processors, a boot control device controlling boot of the plurality of processors, a storage device storing boot data therein, and a shared bus interconnecting the plurality of processors, the boot control device and the storage device. The processors constitute at least one boot processor to which the boot data is to be loaded. The boot control device includes a time slot division unit which produces time slots on the shared bus by multiplexing channels for the processors, and a time sharing control unit which determines a time slot for the boot processor among the time slots produced, and assigns the time slot to the boot processor. The time sharing control unit includes a processor interface part which notifies a time-slot location of the time slot determined, to the boot processor. A bus time-slot setting part notifies the time-slot location to the storage device, allowing reading of the boot data from the storage device and inserting of the boot data into the time slot at the time-slot location among the time slots on the shared bus, so that the boot data is loaded into the boot processor via the shared bus.

Claims

1. A multiprocessor control system including a plurality of processors, a boot control device controlling boot of the plurality of processors, a storage device storing boot data, and a shared bus interconnecting the plurality of processors, the boot control device and the storage device, the plurality of processors constituting at least one boot processor to which the boot data is to be loaded, the boot control device including:

a time slot division unit for producing time slots on the shared bus by multiplexing channels for the plurality of processors; and

a time sharing control unit for determining a time slot for said at least one boot processor among the time slots produced by the time slot division unit, and for assigning the time slot to said at least one boot processor, the time sharing control unit comprising;

processor interface means for notifying a time-slot location of the time slot determined by the time sharing control unit, to said at least one boot processor; and

bus time-slot setting means for notifying the time-slot location to the storage device, the bus time-slot setting means allowing reading of the boot data from the storage device and inserting of the boot data into the time slot at the time-slot location among the time slots on the shared bus, so that the boot data is loaded into said at least one boot processor via the shared bus.

2. The multiprocessor control system according to claim 1, wherein the time sharing control unit notifies a boot start timing to said at least one boot processor by changing a value of a register in said at least one boot processor.

3. The multiprocessor control system according to claim 1, wherein the time sharing control unit notifies a boot start timing to said at least one boot processor by sending an interrupt to said at least one boot processor.

4. The multiprocessor control system according to claim 1, wherein the time sharing control unit notifies a time-slot location of the time slot among the time slots on the shared bus to said at least one boot processor by sending an interrupt to said at least one boot processor.

5. The multiprocessor control system according to claim 1, wherein the time sharing control unit notifies a time-slot number and a time-slot location of the time slot among the time slots on the shared bus to said at least one boot processor by sending an interrupt to said at least one boot processor.

6. The multiprocessor control system according to claim 1, wherein the boot control device includes a processor-status detection unit for detecting processor-status data of the plurality of processors, and the time sharing control unit determines whether executing a boot process for the boot processor is required, based on the processor-status data detected by the processor-status detection unit.

7. The multiprocessor control system according to claim 1, wherein the boot control device includes a first table in which a predetermined boot-active/inactive status of each of the plurality of processors is stored, the time sharing control unit assigning the time slot to said at least one boot processor in accordance with the predetermined boot-active/inactive status of said at least one boot processor read from the first table.

8. The multiprocessor control system according to claim 1, wherein the boot control device includes a second table in which a predetermined boot speed and a predetermined boot-active/inactive status of each of the plurality of processors are stored, the time sharing control unit assigning the time slot to said at least one boot processor in accordance with the predetermined boot speed and the predetermined boot-active/inactive status of said at least one boot processor read from the second table.

9. The multiprocessor control system according to claim 1, wherein the boot control device includes a processor-status detection unit for detecting processor-status data of the plurality of processors by performing polling of the plurality of processors, and the time sharing control unit recognizes a boot request transmitted by one of the plurality of processors based on the processor-status data detected by the processor-status detection unit, the time sharing control unit sending a boot-request response to only said one of the plurality of processors.

10. The multiprocessor control system according to claim 1, wherein each of the plurality of processors notifies a boot speed of the processor to the time sharing control unit when processor-status data of the plurality of processors is detected by the time sharing control unit, the time sharing control unit recognizing a boot speed of said at least one boot processor based on the processor-status data, and assigning the time slot to said at least one boot processor based on the boot speed.

11. The multiprocessor control system according to claim 1, wherein each of the plurality of processors notifies a boot data length of the processor to the time sharing control unit when processor-status data of the plurality of processors is detected by the time sharing control unit, the time sharing control unit recognizing a boot data length of said at least one boot processor based on the processor-status data, and when the time sharing control unit notifies an end time-slot location to the storage device, the storage device outputs a signal, indicating an end of the reading of the boot data, to the time sharing control unit based on the boot data length.

12. The multiprocessor control system according to claim 1, wherein the storage device includes a corresponding number of address counters for the plurality of processors, each of the address counters retaining an address of the boot data for one of the plurality of processors in the storage device, and when the time sharing control unit notifies the time-slot location to the storage device, a corresponding one of the address counters for said at least one boot processor outputs a memory address signal indicating the retained address.

13. The multiprocessor control system according to claim 1, wherein each of the plurality of processors notifies a boot request application type of the processor to the time sharing control unit when processor-status data of the plurality of processors is detected by the time sharing control unit, the time sharing control unit recognizing a boot request application type of said at least one boot processor based on the processor-status data, and assigning the time slot to said at least one boot processor based on the application type.

14. The multiprocessor control system according to claim 13, wherein the storage device includes a plurality of memories which respectively store application programs that can be loaded to said at least one boot processor as the boot data, and when the bus time-slot setting means notifies the time-slot location to the storage device, the bus time-slot setting means allows the storage device to output an enable signal to a corresponding one of the memories that stores an application program indicated by the application type of said at least one boot processor.

15. The multiprocessor control system according to claim 1, wherein a boot process for said at least one boot processor is performed by dividing the boot data into blocks and sequentially loading the blocks of the boot data into said at least one boot processor one by one.

16. The multiprocessor control system according to claim 1, wherein said at least one boot processor detects a data error during a boot process, and when a data error is detected during the boot process, said at least one boot processor notifies the data error to the time sharing control unit, and when the data error notification is received, the time sharing control unit transmits a signal to said at least one boot processor, so that the boot process is stopped by the signal and a complete boot process for said at least one boot processor is restarted.

17. The multiprocessor control system according to claim 1, wherein said at least one boot processor periodically transmits a constant date to the time sharing control unit during a boot process, and the time sharing control unit determines whether the boot process for said at least one boot processor is normally performed, based on the constant data, and when an error during the boot process is detected, the time sharing control unit transmits a signal to said at least one boot processor, so that the boot process is stopped by the signal and a complete boot process for said at least one boot processor is restarted.

18. The multiprocessor control system according to claim 15, wherein, after one block of the boot data is loaded to said at least one boot processor, said at least one boot processor sends a block check result to the time sharing control unit, and when a block check result that indicates a data error is received, the time sharing control unit transmits a signal to said at least one boot processor, so that the boot process is stopped by the signal, and the boot process is restarted from the block at which the data error is detected.

19. The multiprocessor control system according to claim 16, wherein, when the data error is detected again during the restarted boot process, the boot control device holds a channel for said at least one boot processor in an OFF status.

20. The multiprocessor control system according to claim 16, wherein, when the data error is detected again during the restarted boot process, the boot control device transmits a permanent error message related to a channel for said at least one boot processor, to a host system which manages said at least one boot processor.

21. The multiprocessor control system according to claim 16, wherein, when the data error is detected again during the restarted boot process, the boot control device withdraws a channel for said at least one boot processor from the time slot assignment by the time sharing control unit.

22. A boot control device for controlling boot of a plurality of processors connected to a shared bus, the plurality of processors constituting at least one boot processor to which boot data is to be loaded, including:

a time slot division unit for producing time slots on the shared bus by multiplexing channels for the plurality of processors; and

a time sharing control unit for determining a time slot for said at least one boot processor among the time slots produced by the time slot division unit, and for assigning the time slot to said at least one boot processor,

the time sharing control unit comprising;

processor interface means for notifying a time-slot location of the time slot determined by the time sharing control unit, to said at least one boot processor; and

bus time-slot setting means for notifying the time-slot location to the storage device, the bus time-slot setting means allowing reading of the boot data from the storage device and inserting of the boot data into the time slot at the time-slot location among the time slots on the shared bus, so that the boot data is loaded into said at least one boot processor via the shared bus.

23. The boot control device according to claim 22, wherein the boot control device includes an interrupt control unit for sending an interrupt to said at least one boot processor, the time sharing control unit notifies a boot start timing and a time-slot location of the time slot to said at least one boot processor when the interrupt is sent to said at least one boot processor by the interrupt control unit.

24. The boot control device according to claim 22, wherein the boot control device includes a processor-status detection unit for detecting processor-status data of the plurality of processors by performing polling of the plurality of processors, and the time sharing control unit recognizes a boot request transmitted by one of the plurality of processors based on the processor-status data detected by the processor-status detection unit, the time sharing control unit sending a boot-request response to only said one of the plurality of processors.

25. The boot control device according to claim 24, wherein the boot control device further includes a polling control unit for transmitting a polling timing signal to the processor-status detection unit, the processor-status detection unit performing the polling of the plurality of processors in accordance with the polling timing signal to detect the processor-status data of the plurality of processors.

26. The boot control device according to claim 22, wherein the boot control device includes a table in which a predetermined boot-active/inactive status of each of the plurality of processors is stored, the time sharing control unit assigning the time slot to said at least one boot processor in accordance with the predetermined boot-active/inactive status of said at least one boot processor read from the table.

27. The boot control device according to claim 24, wherein the boot control device further includes an error detection unit for detecting whether an error occurs in the processor-status data of the plurality of processors detected by the processor-status detection unit.

28. A boot device including a board on which a plurality of processors, a boot control device controlling boot of the processors, a storage device storing boot data, and a shared bus interconnecting the plurality of processors, the boot control device and the storage device, are installed, the plurality of processors constituting at least one boot processor to which the boot data is to be loaded,

the boot control device including:

a time slot division unit for producing time slots on the shared bus by multiplexing channels for the plurality of processors; and

a time sharing control unit for determining a time slot for said at least one boot processor among the time slots produced by the time slot division unit, and for assigning the time slot to said at least one boot processor,

the time sharing control unit comprising;

processor interface means for notifying a time-slot location of the time slot determined by the time sharing control unit, to said at least one boot processor; and

bus time-slot setting means for notifying the time-slot location to the storage device, the bus time-slot setting means allowing reading of the boot data from the storage device and inserting of the boot data into the time slot at the time-slot location among the time slots on the shared bus, so that the boot data is loaded into said at least one boot processor via the shared bus.

29. The boot device according to claim 28, wherein the board includes a plurality of connection terminals provided thereon in place of the plurality of processors, the plurality of processors being provided outside the board and respectively connected through the plurality of connection terminals to the shared bus.