Method and apparatus for test generation during circuit design

• US 6,347,388 B1
• Filed: 09/21/2000
• Issued: 02/12/2002
• Est. Priority Date: 06/03/1997
• Status: Expired due to Term

• Current Assignee: Verisity Ltd. (Cadence Group)
• Original Assignee: Verisity Ltd. (Cadence Group)
• Inventors: Hollander, Yoav
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Chase, Shelly A
• Application Number:
  US09/668,001
• Time in Patent Office: 509 Days
• Field of Search: 714/33, 714/738, 714/741, 714/739
• US Class Current: 714/739
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/318307 computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
• CPC Class Codes: G01R 31/318314 Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages simulation software G01R31/318357; emulators G06F11/261
• CPC Class Codes: G01R 31/318342 by preliminary fault modelling, e.g. analysis, simulation
• CPC Class Codes: G01R 31/318357 Simulation computer simulation of digital circuits G06F30/3308
• CPC Class Codes: G01R 31/318364 as a result of hardware simulation, e.g. in an HDL environment computer-aided simulation of circuits G06F30/3308
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A method and apparatus are provided for functionally verifying an integrated circuit design. A hardware-oriented verification-specific object-oriented programming language is used to construct and customize verification tests. The language is extensible, and shaped to provide elements for stimulating and observing hardware device models. The invention is platform and simulator-independent, and is adapted for integration with Verilog, VHDL, and C functions. A modular system environment ensures interaction with any simulator through a unified system interface that supports multiple external types. A test generator module automatically creates verification tests from a functional description. A test suite can include any combination of statically and dynamically-generated tests. Directed generation constrains generated tests to specific functionalities. Test parameters are varied at any point during generation and random stability is supported. A checking module can perform any combination of static and dynamic checks. Incremental testing permits gradual development of test suites throughout the design development process. Customized reports of functional coverage statistics and cross coverage reports can be generated. A graphical user interface facilitates the debugging process. High-Level Verification Automation facilities, such as the ability to split and layer architecture and test files, are supported. Both verification environments and test suites can be reused.

Claims

1. An apparatus for functional verification of a device design, comprising:

a test generator module for constraint based random test generation for automatically creating a verification test for said device; and

a checking module for checking the data accuracy of said test when performed on said device;

wherein said design can be verified.

2. The apparatus of claim 1, wherein said device is a simulation of any module, chip, and system.

3. The apparatus of claim 1, further comprising:

an interactive debugging module for displaying data events and the interrelations of said data events, and for permitting modifications to said device design.

4. The apparatus of claim 1, further comprising a reporting module for generating reports regarding said test and said device.

5. The apparatus of claim 4, further comprising a coverage module for showing the distribution of occurrences in a multi-dimensional space thus providing the user with information to locate gaps in the verification process.

6. The apparatus of claim 1, wherein said test generator automatically creates a test from a functional description.

7. The apparatus of claim 1, wherein said apparatus is operable to perform any combination of deterministic tests, random tests, dynamic tests, and static tests.

8. An apparatus for functional verification of a device design, comprising:

a test generator module for constraint based random test generation for automatically creating a verification test for said device, said test generator dynamically creating said test in response to a current state of said device; and

a checking module for checking the data accuracy of said test when performed on said device;

wherein said design can be verified.

9. An apparatus for functional verification of a device design, comprising:

a test generator module for constraint based random test generation for automatically creating a verification test for said device;

a checking module for checking the data accuracy of said test when performed on said device;

wherein said design can be verified; and

a verified specific object-orientated programming language for constructing and customizing said verification tests.

10. The apparatus of claim 9, wherein said verification specific object-orientated programming language is extensible.