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Method and apparatus for test generation during circuit design

  • US 6,347,388 B1
  • Filed: 09/21/2000
  • Issued: 02/12/2002
  • Est. Priority Date: 06/03/1997
  • Status: Expired due to Term
First Claim
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1. An apparatus for functional verification of a device design, comprising:

  • a test generator module for constraint based random test generation for automatically creating a verification test for said device; and

    a checking module for checking the data accuracy of said test when performed on said device;

    wherein said design can be verified.

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