Method and arrangement for rapid silicon prototyping

• US 6,347,395 B1
• Filed: 12/18/1998
• Issued: 02/12/2002
• Est. Priority Date: 12/18/1998
• Status: Expired due to Term

• Current Assignee: Future Link Systems, LLC (Vector Capital Corporation)
• Original Assignee: Koninklijke Philips N.V.
• Inventors: Bapst, Mark, Pontius, Timothy, Payne, Robert
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Siek, Vuthe
• Application Number:
  US09/215,942
• Time in Patent Office: 1,152 Days
• Field of Search: 716/18, 716/1, 716/3, 716/4, 710/100, 710/56, 710/128, 710/62, 710/129
• US Class Current: 716/104
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing

Abstract

A rapid silicon processing arrangement significantly decreases the time from initial design to market introduction. Consistent with one embodiment of the present invention, rapid silicon processing arrangement uses a deconfigurable and extendible reference-chip development platform that includes a programmable device such as an electronically reconfigurable gate array and an off-platform bus for communicating with external devices. The reference-chip development platform can be deconfigured by deselecting communicative activity by one or more of functional block macros. The external devices can be used with the reference-chip development platform to test a hardware representation of the synthesized of the functional block macros in the programmable device within the reference-chip development platform as extended by the off-platform bus. The approach significantly decreases the development time, from initial design to market introduction.

Claims

1. A method for designing a semiconductor circuit arrangement, comprising:

providing a deconfigurable and extendible reference-chip development platform that is programmable, and that includes a programmable circuit and a plurality of functional block macros;

using a collection of functional block macros at least one of which is obtained from the deconfigurable and extendible reference-chip development platform;

extending the deconfigurable and extendible reference-chip development platform, including communicatively coupling at least one external device with the reference-chip development platform, and therein providing an extended deconfigurable and extendible reference-chip development platform that enables co-development and co-validation of hardware and software;

synthesizing a subset of the collection of functional block macros to the programmable circuit; and

validating a hardware representation of the synthesized subset of functional block macros in the programmable circuit within the extended deconfigurable and extendible reference-chip development platform.

2. A method, according to claim 1, further including modifying the subset of the functional block macros and synthesizing the subset of the functional block macros, as modified, to the programmable circuit.

3. A method, according to claim 2, wherein the programmable circuit is hardware reconfigurable and wherein synthesizing the subset of the functional block macros to the programmable circuit includes reconfiguring the programmable circuit.

4. A method, according to claim 3, wherein said validating includes using at least one external device communicatively coupled with the reference-chip development platform.

5. A method, according to claim 4, wherein the programmable circuit includes at least one of:

an FPGA device;

an FPGA plug-in board;

an expansion board; and

an external circuit communicatively coupling via the extended deconfigurable and extendible reference-chip development platform.

6. A method, according to claim 1, wherein at least one of the functional block macros in the subset is reused from the collection of functional block macros.

7. A method, according to claim 6, wherein said at least one reused functional block macro is reused from HDL code into the programmable circuit.

8. A method, according to claim 1, wherein at least one of the functional block macros in the subset is used from a functional block macro obtained from the deconfigurable and extendible reference-chip development platform and reused by retargeting to an ASIC that is developed from the hardware representation.

9. A method, according to claim 8, further including modifying the subset of the functional block macros and synthesizing the subset of the functional block macros, as modified, to the programmable circuit.

10. A method, according to claim 1, wherein at least one of the functional block macros in the subset is reused from the collection of functional block macros, and further including modifying the subset of the functional block macros and synthesizing the subset of the functional block macros, as modified, to the programmable circuit.

11. A system for designing a semiconductor circuit arrangement, comprising:

deconfigurable and extendible means, including a programmable circuit and a plurality of functional block macros, for developing a reference-chip;

means for using a collection of functional block macros at least one of which is obtained from the deconfigurable and extendible means;

means for extending the deconfigurable and extendible means, including means for communicatively coupling at least one external device with the deconfigurable and extendible means, and therein providing an extended deconfigurable and extendible means that enables co-development and co-validation of hardware and software;

means for synthesizing a subset of the collection of functional block macros to the programmable circuit; and

means for validating a hardware representation of the synthesized subset of functional block macros in the programmable circuit within the extended deconfigurable and extendible means.

12. A system, according to claim 11, wherein the means for synthesizing a subset of the collection of functional block macros to the programmable circuit and at least one of the deconfigurable and extendible means and the extended deconfigurable and extendible means, are adapted to modify the subset of the functional block macros and to synthesize the subset of the functional block macros, as modified, to the programmable circuit.

13. A system, according to claim 12, wherein the programmable circuit is hardware reconfigurable and wherein means for synthesizing the subset of the functional block macros to the programmable circuit is adapted to reconfigure the programmable circuit.

14. A system, according to claim 13, wherein the programmable circuit includes at least one of:

an FPGA device;

an FPGA plug-in board;

an expansion board; and

an external circuit communicatively coupling via the extended deconfigurable and extendible means.

15. A system, according to claim 11, wherein at least one of the functional block macros in the subset is reused from the collection of functional block macros.

16. A system, according to claim 15, wherein said at least one reused functional block macro is reused from HDL code into the programmable circuit.

17. A system, according to claim 11, wherein at least one of the functional block macros in the subset is used from a functional block macro obtained from the deconfigurable and extendible means and reused by retargeting to an ASIC that is developed from the hardware representation.

18. A system, according to claim 17, further including means for modifying the subset of the functional block macros and synthesizing the subset of the functional block macros, as modified, to the programmable circuit.

19. A system, according to claim 11, wherein at least one of the functional block macros in the subset is reused from the collection of functional block macros, and further including means for modifying the subset of the functional block macros and synthesizing the subset of the functional block macros, as modified, to the programmable circuit.

20. A system for designing a semiconductor device, comprising:

a deconfigurable and extendible reference-chip development platform that is programmable, and includes a hardware reconfigurable circuit and a plurality of functional block macros;

a collection of functional block macros at least one of which is obtained from the deconfigurable and extendible reference-chip development platform;

an interface circuit configured and arranged to extend the deconfigurable and extendible reference-chip development platform, including a two-way buffer arrangement and logic circuitry adapted to communicatively couple a plurality of external devices with the reference-chip development platform, and therein provide an extended deconfigurable and extendible referencechip development platform that enables co-development and co-validation of hardware and software;

a synthesizer adapted to cause said at least one of the functional block macros to be represented as a configuration of the hardware reconfigurable circuit; and

wherein the extended deconfigurable and extendible reference-chip development platform is adapted to validate the configuration in the hardware reconfigurable circuit within the extended deconfigurable and extendible reference-chip development platform.

21. A system for designing a semiconductor circuit arrangement, comprising:

a deconfigurable and extendible reference-chip development platform that is programmable, and includes a programmable circuit and a plurality of functional block macros;

a collection of functional block macros at least one of which is obtained from the deconfigurable and extendible reference-chip development platform;

an interface circuit configured and arranged to extend the deconfigurable and extendible reference-chip development platform, including a bus and logic circuitry adapted to communicatively couple at least one external device with the reference-chip development platform, and thereby providing an extended deconfigurable and extendible reference-chip development platform that enables co-development and co-validation of hardware and software;

a synthesizer adapted to cause the subset of the collection of functional block macros to be represented as a configuration of the programmable circuit; and

wherein the extended deconfigurable and extendible reference-chip development platform is adapted to validate the configuration in the programmable circuit within the extended deconfigurable and extendible reference-chip development platform.

22. A system, according to claim 21, wherein the synthesizer and at least one of the deconfigurable and extendible reference-chip development platform and the extended deconfigurable and extendible reference-chip development platform, are adapted to modify the subset of the functional block macros and to synthesize the subset of the functional block macros, as modified, to the programmable circuit.

23. A system, according to claim 22, wherein the programmable circuit is hardware reconfigurable and wherein the synthesizer is adapted to reconfigure the programmable circuit.

24. A system, according to claim 23, wherein the programmable circuit includes at least one of:

an FPGA device;

an FPGA plug-in board;

an expansion board; and

an external circuit communicatively coupling via the extended deconfigurable and extendible reference-chip development platform.

25. A system, according to claim 21, wherein at least one of the functional block macros in the subset is reused from the collection of functional block macros.

26. A system, according to claim 25, wherein said at least one reused functional block macro is reused from HDL code into the programmable circuit.

27. A system, according to claim 21, wherein at least one of the functional block macros in the subset is used from a functional block macro obtained from the deconfigurable and extendible reference-chip development platform and reused by retargeting to an ASIC that is developed from the configuration.

28. A system, according to claim 27, further including means for modifying the subset of the functional block macros and wherein the synthesizer synthesizes the subset of the functional block macros, as modified, to the programmable circuit.

29. A system, according to claim 21, wherein at least one of the functional block macros in the subset is reused from the collection of functional block macros, and further including means for modifying the subset of the functional block macros and synthesizing the subset of the functional block macros, as modified, to the programmable circuit.

30. A system, according to claim 21, wherein the extended deconfigurable and extendible reference-chip development platform includes an emulation board.