Monolithic inductor with guard rings

• US 6,348,391 B1
• Filed: 04/26/2000
• Issued: 02/19/2002
• Est. Priority Date: 08/29/1997
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Fattaruso, John W.
• Primary Examiner(s): Dang, Trung
• Assistant Examiner(s): Kebede, Brook
• Application Number:
  US09/559,907
• Time in Patent Office: 664 Days
• Field of Search: 438/381, 438/238, 438/901, 438/329, 438/171, 257/531, 257/532, 257/533, 336/200, 336/232
• US Class Current: 438/381
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

An integrated circuit and method of fabrication are disclosed for achieving electrical isolation between a spiral inductor and an underlying silicon substrate using standard semiconductor manufacturing process flow. A spiral conductor with square windings is formed in metal layer (20) patterned so that straight runs of successive turns (22, 23, 24) overlie corresponding runs of concentric square rings (16, 17, 18) formed in underlying metal layer (14). A unity gain voltage buffer (30) connects each ring (16, 17, 18) with a respective overlying turn (22, 23, 24).

Claims

1. A method of fabricating an inductor monolithically integrated in a semiconductor die, comprising:

providing a semiconductor substrate;

forming a first layer of conductive material on the substrate;

patterning the first conductive layer to form a series of concentric rings;

forming a layer of insulating material on the substrate over the first conductive layer;

forming a second layer of conductive material on the substrate over the insulating layer;

patterning the second conductive layer to form a spiral conductor having successive turns generally superposed and overlying corresponding rings of the first conductive layer, so that at least one second layer turn overlies each first conductive layer ring; and

forming a unity gain voltage buffer on the substrate associated with at least one ring, said buffer having an output connected to the associated ring and an input connected to an overlying turn.

2. The method of claim 1, wherein the buffers are formed as emitter-followers.

3. The method of claim 1, wherein the first conductive layer is patterned to form a series of rectangularly shaped closed rings with straight runs;

and the second conductive layer is patterned to form a rectangular spiral conductor having successive inner to outer turns with straight runs generally superposed and overlying corresponding runs of the first conductor layer rings.

4. The method of claim 2, wherein each buffer has the output connected to a run of the associated ring and the input connected to a corresponding overlying run of the rectangular spiral conductor.