Method to improve adhesion of organic dielectrics in dual damascene interconnects

• US 6,348,407 B1
• Filed: 03/15/2001
• Issued: 02/19/2002
• Est. Priority Date: 03/15/2001
• Status: Expired due to Term

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Inventors: Zhou, Mei Sheng, Xu, Yi, Gupta, Subhash, Chooi, Simon
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): PHAM, THANHHA S
• Application Number:
  US09/805,955
• Time in Patent Office: 341 Days
• Field of Search: 438/638, 438/623, 438/624, 438/622, 438/637, 438/634, 438/639, 438/640, 438/743, 438/778, 438/780, 438/781, 438/787, 438/788, 438/789, 438/790, 438/625, 438/626, 438/627, 438/628, 438/629, 438/633
• US Class Current: 438/637
• CPC Class Codes: H01L 21/31058 of organic layers
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

Abstract

This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the use an alternate etch stop in dual damascene interconnects that improves adhesion between low dielectric constant organic materials. In addition, the etch stop material is a silicon containing material and is transformed into a low dielectric constant material (k=3.5 to 5), which becomes silicon-rich silicon oxide after UV radiation and silylation, oxygen plasma.

Claims

1. A method of fabricating damascene comprising:

providing a semiconductor substrate;

providing patterned metal wiring embedded in an insulator over the semiconductor substrate;

depositing a passivation layer over said patterned metal wiring;

depositing a first low dielectric constant material layer upon said passivation layer;

coating a silicon containing adhesion layer on the first low dielectric constant material layer;

exposing said silicon containing adhesion layer to UV radiation;

exposing said silicon containing adhesion layer to a silylation and oxygen plasma process;

depositing a second low dielectric constant material layer upon said silicon containing adhesion layer;

providing patterning and etching the second and first low dielectric constant material layers, the silicon containing adhesion layer, and the passivation layer to form trench/via openings extending to the patterned metal wiring;

depositing a blanket layer of barrier metal over the semiconductor substrate and into the trench/via opening;

depositing a blanket conducting copper seed layer over the barrier metal;

depositing by electroplating or electroless plating conducting thick copper upon the copper seed layer.

2. The method of claim 1, wherein said semiconductor substrate is selected from the group consisting of single crystal silicon, silicon-on-insulator (SOI), silicon-germanium (SiGe) with semiconductor devices, interconnect wiring and contact vias over the substrate.

3. The method of claim 1, wherein said layer of first low dielectric constant material layer selected from the group consisting of either organic based materials or carbon doped SiO₂ materials, wherein organic based materials are selected from the group consisting of organic polymers comprised of 100% carbon, carbon with one or more of the following elements:

hydrogen, fluorine, sulfur, nitrogen, bromine, while carbon doped SiO₂ materials are selected from the group consisting of alkyl silsesquioxane, aryl silsesquioxane, CORAL (from Novellus), Black Diamond (from Applied Materials).

4. The method of claim 1, wherein said layer of second low dielectric constant material layer selected from the group consisting of either organic based materials or carbon doped SiO₂ materials, wherein organic based materials are selected from the group consisting of organic polymers comprised of 100% carbon, carbon with one or more of the following elements:

hydrogen, fluorine, sulfur, nitrogen, bromine, while carbon doped SiO₂ materials are selected from the group consisting of alkyl silsesquioxane, aryl silsesquioxane, CORAL (from Novellus), Black Diamond (from Applied Materials).

5. The method of claim 1, wherein said silicon containing adhesion layer is comprised of a silicon containing material selected from the group consisting of TSI resist that is transformed into silicon-rich silicon oxide by subsequent processing steps including silylation, exposure to UV radiation, oxygen plasma treatment and has a low dielectric constant between 3.5 to 5.

6. The method of claim 1, wherein said silicon containing adhesion layer is exposed forming an exposed layer, which is comprised of a silicon-rich material, whereby the UV wavelength ranges from 436 to 100 nm, with an exposure time between 1 sec to 5 min, and furthermore, a pre-silylation bake at between 50 to 400°

C. promotes cross-linking of the exposed layer.

7. The method of claim 1, wherein said silicon containing adhesion layer is comprised of TSI resist and is exposed to said silylation, wherein the silylation conditions are as follows:

an inert gas, nitrogen, is bubbled in liquid HMDS (hexamethyldisilazane), thus, transporting HMDS in the vapor phase to TSI resist in a reaction chamber, wherein the semiconductor substrate wafer is heated to between 40 to 150°

C., or alternately, using solutions of 10% HMDS (hexamethyldisilazane) in xylene causes the resist to become silylated.

8. The method of claim 1, wherein said silicon containing adhesion layer is comprised of TSI resist and is exposed to said oxygen plasma process under conditions as follows:

the oxygen plasmas process is performed at temperatures between 40 to 400°

C., at pressures between 1 milliTorr to 50 Torr using oxygen gas, oxygen flow rates are from 100 sccm to 50,000 sccm, power settings of between 100 to 2,000 Watts with RF or microwave capacitatively coupled to the plasma, with the addition of forming gas (96% nitrogen, 4% hydrogen) added to the oxygen gas, to aid in the dissociation of oxygen.

9. The method of claim 1, wherein said barrier metal is selected from the group consisting of tantalum, tantalum nitride, titanium nitride, ternary metal silicon nitride;

and the barrier metal has a thickness between approximately 50 to 2,000 Angstroms.

10. The method of claim 1, wherein said copper seed layer is deposited over the barrier metal by chemical vapor deposition (CVD) or by sputtering, physical vapor deposition (PVD), in a thickness range from 50 to 2,000 Angstroms.

11. The method of claim 1, wherein said conducting thick copper is in a thickness range from 1 to 10 microns.

12. A method of fabricating damascene trench/via using a silicon containing adhesion layer comprising:

providing a semiconductor substrate;

providing patterned metal wiring embedded in an insulator over the semiconductor substrate;

depositing a passivation layer over said patterned metal wiring;

depositing a first low dielectric constant material layer upon said passivation layer;

coating a silicon containing adhesion layer on the first low dielectric constant material layer;

exposing said silicon containing adhesion layer to UV radiation;

exposing said silicon containing adhesion layer to a silylation and oxygen plasma process;

depositing a second low dielectric constant material layer upon said silicon containing adhesion layer;

providing patterning and etching of the second and first low dielectric constant material layers, the adhesion layer, and the passivation layer to form trench/via opening extending to the patterned metal wiring;

depositing a blanket layer of barrier metal over the semiconductor substrate and into the trench/via opening;

depositing a blanket conducting copper seed layer over the barrier metal;

depositing by electroplating or electroless plating conducting thick copper upon the copper seed layer;

chemical-mechanical polishing and planarizing to remove excess thick copper, excess copper seed layer and excess barrier metal thereby forming an inlaid interconnect and contact via to said patterned metal wiring with said barrier metal lining the trench/via opening.

13. The method of claim 12, wherein said semiconductor substrate is selected from the group consisting of single crystal silicon, silicon-on-insulator (SOI), silicon-germanium (SiGe) with semiconductor devices, interconnect wiring and contact vias over the substrate.

14. The method of claim 12, wherein said layer of first low dielectric constant material layer selected from the group consisting of either organic based materials or carbon doped SiO₂ materials, wherein organic based materials are selected from the group consisting of organic polymers comprised of 100% carbon, carbon with one or more of the following elements:

hydrogen, fluorine, sulfur, nitrogen, bromine, while carbon doped SiO₂ materials are selected from the group consisting of alkyl silsesquioxane, aryl silsesquioxane, CORAL (from Novellus), Black Diamond (from Applied Materials).

15. The method of claim 12, wherein said layer of second low dielectric constant material layer selected from the group consisting of either organic based materials or carbon doped SiO₂ materials, wherein organic based materials are selected from the group consisting of organic polymers comprised of 100% carbon, carbon with one or more of the following elements:

hydrogen, fluorine, sulfur, nitrogen, bromine, while carbon doped SiO₂ materials are selected from the group consisting of alkyl silsesquioxane, aryl silsesquioxane, CORAL (from Novellus), Black Diamond (from Applied Materials).

16. The method of claim 12, wherein said silicon containing adhesion layer is comprised of a silicon containing material selected from the group consisting of TSI resist that is transformed into silicon-rich silicon oxide by subsequent processing steps including silylation, exposure to UV radiation, oxygen plasma treatment and has a low dielectric constant between 3.5 to 5.

17. The method of claim 12, wherein said silicon containing adhesion layer is exposed forming an exposed layer, which is comprised of a silicon-rich material, whereby the UV wavelength ranges from 436 to 100 nm, with an exposure time between 1 sec to 5 min, and furthermore, a pre-silylation bake at between 50 to 400°

C. promotes cross-linking of the exposed layer.

18. The method of claim 12, wherein said silicon containing adhesion layer is comprised of TSI resist and is exposed to said silylation, wherein the silylation conditions are as follows:

an inert gas, nitrogen, is bubbled in liquid HMDS (hexamethyldisilazane), thus, transporting HMDS in the vapor phase to TSI resist in a reaction chamber, wherein the semiconductor substrate wafer is heated to between 40 to 150°

C., or alternately, using solutions of 10% HMDS (hexamethyldisilazane) in xylene causes the resist to become silylated.

19. The method of claim 12, wherein said silicon containing adhesion layer is comprised of TSI resist and is exposed to said oxygen plasma process under conditions as follows:

the oxygen plasmas process is performed at temperatures between 40 to 400°

C., at pressures between 1 milliTorr to 50 Torr using oxygen gas, oxygen flow rates are from 100 sccm to 50,000 sccm, power settings of between 100 to 2,000 Watts with RF or microwave capacitatively coupled to the plasma, with the addition of forming gas (96% nitrogen, 4% hydrogen) added to the oxygen gas, to aid in the dissociation of oxygen.

20. The method of claim 12, wherein said barrier metal is selected from the group consisting of tantalum, tantalum nitride, titanium nitride, ternary metal silicon nitride;

and the barrier metal has a thickness between approximately 50 to 2,000 Angstroms.

21. The method of claim 12, wherein said copper seed layer is deposited over the barrier metal by chemical vapor deposition (CVD) or by sputtering, physical vapor deposition (PVD), in a thickness range from 50 to 2,000 Angstroms.

22. The method of claim 12, wherein said conducting thick copper is in a thickness range from 1 to 10 microns.

23. A method of fabricating damascene trench/via using a silicon containing low dielectric constant adhesion layer, which is an alternate etch stop in dual damascene, in the fabrication of semiconductor devices, comprising:

providing a semiconductor substrate with semiconductor devices within the semiconductor substrate;

providing patterned metal wiring embedded in an insulator over the semiconductor substrate;

depositing a passivation layer over said patterned metal wiring;

depositing a first low dielectric constant material layer, which is organic-based or carbon doped SiO₂, upon said passivation layer;

coating a silicon containing adhesion layer on the first low dielectric constant material layer;

exposing said silicon containing adhesion layer to UV radiation, forming a silicon-rich material layer;

exposing said silicon containing adhesion layer to a silylation and oxygen plasma process, transforming said silicon containing adhesion layer into a silicon-rich silicon oxide;

depositing a second low dielectric constant material layer, which is organic-based or carbon doped SiO₂, upon said silicon containing adhesion layer;

providing patterning and etching the second and first low dielectric constant material layers, the silicon containing adhesion layer, and the passivation layer to form trench/via opening extending to the patterned metal wiring;

depositing a blanket layer of barrier metal over the semiconductor substrate and into the trench/via opening;

depositing a blanket conducting copper seed layer over the barrier metal;

depositing by electroplating or electroless plating conducting thick copper upon the copper seed layer;

chemical-mechanical polishing and planarizing to remove excess thick copper, excess copper seed layer and excess barrier metal thereby forming an inlaid interconnect and contact via to said patterned metal wiring with said barrier metal lining the trench/via opening; and

depositing and forming a cap layer over the top of the second low dielectric constant material layer, thus passivating the dual damascene.

24. The method of claim 23, wherein said semiconductor substrate is selected from the group consisting of single crystal silicon, silicon-on-insulator (SOI), silicon-germanium (SiGe) with semiconductor devices, interconnect wiring and contact vias over the substrate.

25. The method of claim 23, wherein said layer of first low dielectric constant material layer selected from the group consisting of either organic based materials or carbon doped SiO₂ materials, wherein organic based materials are selected from the group consisting of organic polymers comprised of 100% carbon, carbon with one or more of the following elements:

hydrogen, fluorine, sulfur, nitrogen, bromine, while carbon doped SiO₂ materials are selected from the group consisting of alkyl silsesquioxane, aryl silsesquioxane, CORAL (from Novellus), Black Diamond (from Applied Materials).

26. The method of claim 23, wherein said layer of second low dielectric constant material layer selected from the group consisting of either organic based materials or carbon doped SiO₂ materials, wherein organic based materials are selected from the group consisting of organic polymers comprised of 100% carbon, carbon with one or more of the following elements:

hydrogen, fluorine, sulfur, nitrogen, bromine, while carbon doped SiO₂ materials are selected from the group consisting of alkyl silsesquioxane, aryl silsesquioxane, CORAL (from Novellus), Black Diamond (from Applied Materials).

27. The method of claim 23, wherein said silicon containing adhesion layer is comprised of a silicon containing material selected from the group consisting of TSI resist that is transformed into silicon-rich silicon oxide by subsequent processing steps including silylation, exposure to UV radiation, oxygen plasma treatment and has a low dielectric constant between 3.5 to 5.

28. The method of claim 23, wherein said silicon containing adhesion layer is exposed forming an exposed layer, which is comprised of a silicon-rich material, whereby the UV wavelength ranges from 436 to 100 nm, with an exposure time between 1 sec to 5 min, and furthermore, a pre-silylation bake at between 50 to 400°

C. promotes cross-linking of the exposed layer.

29. The method of claim 23, wherein said silicon containing adhesion layer is comprised of TSI resist and is exposed to said silylation, wherein the silylation conditions are as follows:

an inert gas, nitrogen, is bubbled in liquid HMDS (hexamethyldisilazane), thus, transporting HMDS in the vapor phase to TSI resist in a reaction chamber, wherein the semiconductor substrate wafer is heated to between 40 to 150°

C., or alternately, using solutions of 10% HMDS (hexamethyldisilazane) in xylene causes the resist to become silylated.

30. The method of claim 23, wherein said silicon containing adhesion layer is comprised of TSI resist and is exposed to said oxygen plasma process under conditions as follows:

the oxygen plasmas process is performed at temperatures between 40 to 400°

C., at pressures between 1 milliTorr to 50 Torr using oxygen gas, oxygen flow rates are from 100 sccm to 50,000 sccm, power settings of between 100 to 2,000 Watts with RF or microwave capacitatively coupled to the plasma, with the addition of forming gas (96% nitrogen, 4% hydrogen) added to the oxygen gas, to aid in the dissociation of oxygen.

31. The method of claim 23, wherein said barrier metal is selected from the group consisting of tantalum, tantalum nitride, titanium nitride, ternary metal silicon nitride;

and the barrier metal has a thickness between approximately 50 to 2,000 Angstroms.

32. The method of claim 23, wherein said copper seed layer is deposited over the barrier metal by chemical vapor deposition (CVD) or by sputtering, physical vapor deposition (PVD), in a thickness range from 50 to 2,000 Angstroms.

33. The method of claim 23, wherein said conducting thick copper is in a thickness range from 1 to 10 microns.

34. The method of claim 23, wherein said cap layer is selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbide and is deposited by chemical vapor deposition (CVD), in a thickness range from 50 to 5,000 Angstroms.