Frequency control of hysteretic power converter by adjusting hystersis levels

• US 6,348,780 B1
• Filed: 09/22/2000
• Issued: 02/19/2002
• Est. Priority Date: 09/22/2000
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Grant, David
• Primary Examiner(s): Vu, Bao Q.
• Application Number:
  US09/668,842
• Time in Patent Office: 515 Days
• Field of Search: 323/222, 323/223, 323/282, 323/286, 323/284, 323/283
• US Class Current: 323/222
• CPC Class Codes: H02M 1/0012 Control circuits using digital or numerical techniques in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators

Abstract

A power converter is comprised of a hysteretic controller including a feedback circuit that monitors the output frequency of the controller, compares it to a reference generated either internally or externally by the user, and then adjusts the hysteresis of the controller accordingly. The adjusted hysteresis levels will then cause the switching frequency to either increase or decrease thereby controlling the switching frequency of the power supply controller and maintaining it at a desired level.

Claims

1. A power converter control circuit comprising:

a controller circuit connected to control the generation of an output voltage based on set hysteresis levels of the output voltage;

a feedback circuit connected to the controller circuit, the feedback circuit receiving a first signal representative of the switching frequency of the controller and outputting a correction signal to the controller to adjust the set hysteresis levels.

2. The power converter control circuit of claim 1, wherein the controller circuit receives a second signal representative of the output voltage, the controller circuit generating the output voltage based on the set hysteresis levels by comparing the second signal with the set hysteresis levels to determine if the output voltage has reached the set hysteresis levels.

3. The power converter control circuit of claim 1, wherein the feedback circuit generates the correction signal based on a comparison of the first signal with a reference.

4. The power converter control circuit of claim 3, wherein the first signal is converted to a voltage representation prior to the comparison with the reference and the reference is a voltage reference.

5. The power converter control circuit of claim 3, wherein the power converter control circuit is located on a single integrated circuit and wherein the first signal is converted to a current representation prior to the comparison with the reference and the reference is a current reference generated on the single integrated circuit.

6. The power converter control circuit of claim 1, wherein the feedback circuit comprises an integrator including an inverting input node and a noninverting input node.

7. The power converter control circuit of claim 6, wherein the feedback circuit further includes a charge dispensing circuit coupled to the inverting node of the integrator.

8. The power converter control circuit of claim 1, wherein the feedback circuit includes a phase lock loop (PLL) circuit.

9. The power converter control circuit of claim 8, wherein power converter control circuit is located on a single integrated circuit and the feedback circuit further includes an oscillator located on the integrated circuit and coupled to the input of the phase lock loop (PLL) circuit.

22. The power converter control circuit of claim 3, wherein the power converter control circuit is located on a single integrated circuit and wherein the reference is generated on the integrated circuit.

23. The power converter control circuit of claim 3, wherein the power converter control circuit is located on a single integrated circuit and wherein the reference is supplied external to the integrated circuit.

24. The power converter control circuit of claim 23, wherein the first signal is converted to a current representation prior to the comparison with the reference and the reference is a current reference.

25. The power converter control circuit of claim 22, wherein the first signal is converted to a voltage representation prior to the comparison with the reference and the reference is a voltage reference.

26. The power converter control circuit of claim 23, wherein the first signal is converted to a voltage representation prior to the comparison with the reference and the reference is a voltage reference.

10. A power converter control circuit comprising:

a controller circuit connected to control the generation of an output voltage, the controller receiving a feedback signal from the output voltage and controlling the output voltage based on a comparison of the output voltage with set hysteresis levels;

a frequency feedback circuit connected to the controller, the frequency feedback circuit receiving a signal representative of the switching frequency of the controller, comparing the signal to a reference, and outputting a signal to the controller in order to adjust the set hysteresis levels.

11. The power converter control circuit of claim 10, wherein the frequency feedback circuit includes an integrator circuit to compare the signal to the reference.

12. The power converter control circuit of claim 11, wherein the power converter control circuit is formed on a single integrated circuit and the reference is generated on the integrated circuit.

13. The power converter control circuit of claim 10, wherein the power converter control circuit is formed on a single integrated circuit and the reference is supplied external to the integrated circuit.

14. The power converter control circuit of claim 10, wherein the frequency feedback circuit includes a phase lock loop (PLL) circuit.

15. The power converter control circuit of claim 14, wherein the power coverter circuit is located on a single integrated circuit and the frequency feedback circuit further includes an oscillator located on the integrated circuit and coupled to the input of the phase lock loop (PLL) circuit.

27. The power converter control circuit of claim 12, wherein the signal representative of the switching frequency is converted to a voltage representation prior to the comparison with the reference and the reference is a voltage reference.

28. The power converter control circuit of claim 13, wherein the signal representative of the switching frequency is converted to a voltage representation prior to the comparison with the reference and the reference is a voltage reference.

29. The power converter control circuit of claim 12, wherein the signal representative of the switching frequency is converted to a current representation prior to the comparison with the reference and the reference is a current reference.

30. The power converter control circuit of claim 13, wherein the signal representative of the switching frequency is converted to a current representation prior to the comparison with the reference and the reference is a current reference.

16. A method of controlling the switching frequency of a regulator controller comprising:

generating an output voltage on an output voltage line by comparing the output voltage with set hysteresis levels and based on the comparison generating signals to alternately drive high and low drivers coupled to the output voltage line;

outputting a feedback signal representative of the switching frequency of the high and low drivers;

comparing the feedback signal to a reference;

generating an error signal representative of the difference between the feedback signal and the reference;

using the error signal to adjust the set hysteresis levels.

17. The method of claim 16, wherein the step of comparing the feedback signal to a reference is performed using an integrator.

18. The method of claim 16, wherein the step of comparing the feedback signal to a reference is performed using a phase lock loop (PLL) circuit.

19. The method of claim 16, wherein the phase lock loop (PLL) circuit is a digital phase lock loop (PLL) circuit.

20. The method of claim 16, wherein all of the steps are performed on a single integrated circuit and the reference is also generated on the integrated circuit.

21. The method of claim 16, wherein all of the steps are performed on a single integrated circuit and the reference is supplied externally to the integrated circuit.