Digital variable-delay circuit having voltage-mixing interpolator and methods of testing input/output buffers using same

• US 6,348,826 B1
• Filed: 06/28/2000
• Issued: 02/19/2002
• Est. Priority Date: 06/28/2000
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Spitz, Jonathan N., Sandhinti, Michael S., Mooney, Stephen R., Martin, Aaron K., Haycock, Matthew B.
• Primary Examiner(s): Le, Dinh T.
• Application Number:
  US09/605,624
• Time in Patent Office: 601 Days
• Field of Search: 327/231, 327/256, 327/257, 327/356, 327/357, 327/359, 327/270, 327/261
• US Class Current: 327/270
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G01R 31/31712 Input or output aspects
• CPC Class Codes: G01R 31/31715 Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
• CPC Class Codes: G01R 31/318525 Test of flip-flops or latches
• CPC Class Codes: G01R 31/31853 Test of registers
• CPC Class Codes: G01R 31/31922 Timing generation or clock distribution G01R31/3191 takes precedence
• CPC Class Codes: H03K 2005/00065 by current control, e.g. by parallel current control transistors
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0818 the controlled phase shifter comprising coarse and fine delay or phase-shifting means

Abstract

A variable-delay circuit on an integrated circuit is used to delay a periodic strobe signal. In normal operation, the strobe signal can be shifted 90 degrees to center it within a data bit cell. In test mode, it can also be shifted up to 270 degrees in N increments to measure the effective input latch setup and hold timings. The variable-delay circuit comprises a voltage-mixing interpolator circuit to produce phase delays in N increments. The variable-delay circuit can incorporate an existing delay locked loop. Also described are an electronic system, a data processing system, and various methods of performing on-chip testing and calibration.

Claims

1. An interpolator circuit for providing a controllable phase offset comprising:

an output terminal at which the controllable phase offset is provided;

a delay circuit comprising an input node to receive a periodic signal, and an output node to generate an output signal having a fixed phase relationship with respect to the periodic signal; and

a logic circuit to mix the periodic signal with the output signal to produce the controllable phase offset, wherein the logic circuit comprises;

a first plurality of transmission gates, each having a first node coupled to the input node, a control node, and a second node coupled to the output terminal; and

a second plurality of transmission gates, each having a first node coupled to the output node, a control node, and a second node coupled to the output terminal.

2. The interpolator circuit of claim 1, wherein the control nodes of the first and second plurality of transmission gates are configured to receive first and second control codes, respectively.

3. An interpolator circuit for providing a controllable phase offset comprising:

an output terminal at which the controllable phase offset is provided;

a delay circuit comprising an input node to receive a periodic signal, and an output node to generate an output signal having a fixed phase relationship with respect to the periodic signal;

a first plurality of transmission gates, each having a first node coupled to the input node, a control node, and a second node coupled to the output terminal; and

a second plurality of transmission gates, each having a first node coupled to the output node, a control node, and a second node coupled to the output terminal.

4. The interpolator circuit of claim 3, wherein the control nodes of the first and second plurality of transmission gates are configured to receive first and second control codes, respectively.

5. The interpolator circuit of claim 4, wherein relative contributions of the periodic signal and of the output signal to the controllable phase offset can be varied depending upon the first and second control codes.

6. A variable-delay circuit comprising:

an input terminal to receive a periodic signal;

an output terminal to provide an output signal having a fixed phase relationship with respect to the periodic signal;

a delay line coupled to the input terminal to receive the periodic signal, and having a tap to provide a first intermediate signal having a fixed phase relationship with respect to the periodic signal; and

an interpolator circuit coupled to the tap to provide a controllable phase offset and comprising;

an output junction coupled to the output terminal;

a delay circuit, having an input node to receive the first intermediate signal, and having an output node to generate a second intermediate signal having a fixed phase relationship with respect to the first intermediate signal; and

a logic circuit to mix the first intermediate signal with the second intermediate signal to produce the controllable phase offset, wherein the logic circuit comprises;

a first plurality of transmission gates, each having a first node coupled to the input node, a control node, and a second node coupled to the output junction; and

a second plurality of transmission gates, each having a first node coupled to the output node, a control node, and a second node coupled to the output junction.

7. The variable-delay circuit of claim 6, wherein the control nodes of the first and second plurality of transmission gates are configured to receive first and second control codes, respectively.

8. An integrated circuit having at least one variable-delay circuit comprising

a first terminal to receive a periodic signal;

a second terminal to provide an output signal having a fixed phase relationship with respect to the periodic signal;

a delay line coupled to the first terminal to receive the periodic signal, and having a tap to provide a first intermediate signal having a fixed phase relationship with respect to the periodic signal; and

an interpolator circuit coupled to the tap to provide a controllable phase offset and comprising;

an output junction coupled to the second terminal;

a delay circuit, having an input node to receive the first intermediate signal, and having an output node to generate a second intermediate signal having a fixed phase relationship with respect to the first intermediate signal; and

a logic circuit to mix the first intermediate signal with the second intermediate signal to produce the controllable phase offset, wherein the logic circuit comprises;

a first plurality of transmission gates, each having a first node coupled to the input node, a control node, and a second node coupled to the output junction; and

a second plurality of transmission gates, each having a first node coupled to the output node, a control node, and a second node coupled to the output junction.

9. The integrated circuit of claim 8, wherein the control nodes of the first and second plurality of transmission gates are configures to receive first and second control codes, respectively.

10. The integrated circuit of claim 9 wherein the delay line generates a phase delay of known value at the tap of the delay line, the integrated circuit further comprising:

a phase detector responsive to the phase delay of known value and to the output signal for determining a combination of the first and second control codes which, when received by the first and second plurality of transmission gates, respectively, cause the interpolator circuit to produce an output signal having the closest phase relationship to the phase delay of known value.

11. An electronic system having at least one variable-delay circuit comprising:

a first terminal to receive a periodic signal;

a second terminal to provide an output signal having a fixed phase relationship with respect to the periodic signal;

a delay line coupled to the first terminal to receive the periodic signal, and having a tap to provide a first intermediate signal having a fixed phase relationship with respect to the periodic signal; and

an interpolator circuit coupled to the tap to provide a controllable phase offset and comprising;

an output junction coupled to the second terminal;

a delay circuit, having an input node to receive the first intermediate signal, and having an output node to generate a second intermediate signal having a fixed phase relationship with respect to the first intermediate signal; and

a logic circuit to mix the first intermediate signal with the second intermediate signal to produce the controllable phase offset, wherein the logic circuit comprises;

a first plurality of transmission gates, each having a first node coupled to the input node, a control node, and a second node coupled to the output junction; and

a second plurality of transmission gates, each having a first node coupled to the output node, a control node, and a second node coupled to the output junction.

12. The electronic system of claim 11, wherein the control nodes of the first and second plurality of transmission gates are configured to receive first and second control codes, respectively.

13. A data processing system comprising:

a plurality of components;

a bus coupling the components; and

wherein at least one component includes at least one variable-delay circuit comprising;

a first terminal to receive a periodic signal;

a second terminal to provide an output signal having a fixed phase relationship with respect to the periodic signal;

a delay line coupled to the first terminal to receive the periodic signal, and having a tap to provide a first intermediate signal having a fixed phase relationship with respect to the periodic signal; and

an interpolator circuit coupled to the tap to provide a controllable phase offset and comprising;

an output junction coupled to the second terminal;

a delay circuit, having an input node to receive the first intermediate signal, and having an output node to generate a second intermediate signal having a fixed phase relationship with respect to the first intermediate signal; and

a logic circuit to mix the first intermediate signal with the second intermediate signal to produce the controllable phase offset, wherein the components are from the group consisting of a processor, chipset logic, and an external memory.

14. A data processing system comprising:

a plurality of components;

a bus coupling the components; and

wherein at least one component includes at least one variable-delay circuit comprising;

a first terminal to receive a periodic signal;

a second terminal to provide an output signal having a fixed phase relationship with respect to the periodic signal;

a delay line coupled to the first terminal to receive the periodic signal, and having a tap to provide a first intermediate signal having a fixed phase relationship with respect to the periodic signal; and

an interpolator circuit coupled to the tap to provide a controllable phase offset and comprising;

an output junction coupled to the second terminal;

a delay circuit, having an input node to receive the first intermediate signal, and having an output node to generate a second intermediate signal having a fixed phase relationship with respect to the first intermediate signal; and

a logic circuit to mix the first intermediate signal with the second intermediate signal to produce the controllable phase offset, wherein the logic circuit comprises;

a first plurality of transmission gates, each having a first node coupled to the input node, a control node, and a second node coupled to the output junction;

a second plurality of transmission gates, each having a first node coupled to the output node, a control node, and a second node coupled to the output junction; and

wherein the control nodes of the first and second plurality of transmission gates are configured to receive first and second control codes, respectively.

15. A method for performing loopback testing of an integrated circuit having at least one input/output circuit to generate and to receive a data signal and a strobe signal, the integrated circuit further having at least one delay line, the delay line being coupled to the at least one input/output circuit, the method comprising:

using the delay line in normal operation to position an edge of the strobe signal with respect to a data cell of the data signal; and

using the same delay line in loopback testing to shift the edge of the strobe signal with respect to the data cell of the data signal.

16. The method of claim 15, wherein the integrated circuit further comprises an interpolator circuit coupled to the delay line, the method further comprising:

the delay line shifting the phase of a strobe signal input thereto to generate a strobe signal with a phase offset; and

in loopback testing, using the-interpolator circuit to vary the phase offset of the strobe signal.

17. The method of claim 16, and further comprising:

controlling the interpolator circuit in response to a plurality of control codes, each of which corresponds to a different phase offset.

18. The method of claim 17, wherein the interpolator circuit comprises a logic circuit responsive to the plurality of control codes, and further comprising:

the logic circuit mixing the strobe signal with a delayed strobe signal to generate the strobe signal with a phase offset.

19. The method of claim 18, wherein the logic circuit comprises a plurality of transmission gates each of which has a control gate, and further comprising:

each control gate receiving a portion of the plurality of control codes.

20. In an integrated circuit comprising at least one input/output circuit to receive a data signal and a strobe signal, and further comprising at least one delay line coupled to the at least one input/output circuit to shift a phase of the strobe signal and to generate a strobe signal with a phase offset, the method comprising:

enabling an interpolator circuit coupled to the delay line; and

using the interpolator circuit to vary the phase offset of the strobe signal.

21. The method of claim 20, and further comprising:

controlling the interpolator circuit in response to a plurality of control codes, each of which corresponds to a different phase offset.

22. The method of claim 21, wherein the interpolator circuit comprises a logic circuit responsive to the plurality of control codes, and further comprising:

the logic circuit mixing the strobe signal with a delayed strobe signal to generate the strobe signal with a phase offset.

23. The method of claim 22, wherein the logic circuit comprises a plurality of transmission gates each having a control gate, and further comprising:

each control gate receiving a portion of the plurality of control codes.

24. The method of claim 20, further comprising:

varying the phase offset to align the strobe signal with respect to a data cell of the data signal.

25. The method of claim 20, wherein the integrated circuit further comprises a phase detector, and wherein the at least one delay line generates a phase offset of known value at a tap of the delay line, the method further comprising:

the phase detector comparing the phase offset of known value with the phase offset at an output of the interpolator circuit.