Semiconductor device with constant current source circuit not influenced by noise

• US 6,348,835 B1
• Filed: 05/26/2000
• Issued: 02/19/2002
• Est. Priority Date: 05/27/1999
• Status: Expired due to Term

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: NEC Corporation
• Inventors: Sato, Tomohiko, Tsukada, Shyuichi
• Primary Examiner(s): Zweizig, Jeffrey
• Application Number:
  US09/578,500
• Time in Patent Office: 634 Days
• Field of Search: 323/315, 327/530, 327/538, 327/543
• US Class Current: 327/543
• CPC Class Codes: G05F 3/262 using field-effect transistors only

Abstract

A semiconductor device with a constant current source circuit includes a current mirror circuit including first and second transistors, third and fourth transistors, a first resistor and a potential change transferring section. In the current mirror circuit, the first and second transistors are connected to a line of a power supply potential and supply first and second currents, respectively. Each of the third and fourth transistors has a control electrode and first and second electrodes. The control electrode is operatively coupled to a first potential. The first electrode and the control electrode in the third transistor are connected to a first node, and the control electrode of the fourth transistor is connected to the first node. The third and fourth transistors receive the first and second currents at the first electrodes from the current mirror circuit, respectively. The first resistor is connected between the second electrode of the fourth transistor and a second node. The potential change transferring section is connected to a second potential and the second node such that a change of potential difference between the first potential and the second potential is transferred to the second electrodes of the third and fourth transistors.

Claims

1. A semiconductor device with a constant current source circuit comprising:

a current mirror circuit including first and second transistors, connected to a line of a power supply potential, and respectively supplying first and second currents;

third and fourth transistors, each of which has a control electrode and first and second electrodes, and said control electrode is operatively coupled to a first potential, wherein said first electrode and said control electrode in said third transistor are connected to a first node, said control electrode of said fourth transistor is connected to said first node, and said third and fourth transistors receive said first and second currents at said first electrodes from said current mirror circuit, respectively;

a first resistor connected between said second electrode of said fourth transistor and a second node; and

a potential change transferring section connected to a second potential and said second node such that a change of potential difference between said first potential and said second potential is transferred to said second electrodes of said third and fourth transistors.

2. A semiconductor device according to claim 1, wherein said potential change transferring section holds a potential difference between said control electrode and said second electrode in each of said third and fourth transistors when said potential difference between said first potential and said second potential changes.

3. A semiconductor device according to claim 1, wherein said second electrode of said third transistor connected directly to said second node,

wherein said potential change transferring section includes a second resistor connected between said second node and said second potential.

4. A semiconductor device according to claim 3, wherein said potential change transferring section further includes a first capacitor connected between said second node and at least one of said first potential and said second potential.

5. A semiconductor device according to claim 4, wherein a combination of said first capacitor and said second resistor functions as a low pass filter with a cut-off frequency of 1/{2π

R₂(C_(A)+Co)},

where R₂ is a resistance of said second resistor, C_(A) is a parasitic capacitance of said second node, and Co is a junction capacitance between a diffusion layer and a substrate on which said first to fourth transistors are formed.

6. A semiconductor device according to claim 5, wherein said diffusion layer is formed to surround a region where said third and fourth transistors are formed.

7. A semiconductor device according to claim 1, wherein said potential change transferring section comprises a low pass filter interconnected between said second node, said first potential, and said second potential.

8. A semiconductor device according to claim 1, wherein said potential change transferring section includes:

a third resistor connected between said second electrode of said third transistor and said second node, said second node being connected directly to said second potential.

9. A semiconductor device according to claim 8, wherein said third resistor has a resistance which meets a relation of (I₂R₁−

I₁R₃)=constant,

where I₁ and I₂ are said first and second currents, R₁ is a resistance of said first resistor and R₃ is a resistance of said third resistor.

10. A semiconductor device according to claim 1, wherein said potential change transferring section includes:

a fourth resistor connected between said second electrode of said third transistor and said second node;

a second capacitor connected between said first potential and said second electrode of said fourth transistor; and

a third capacitor connected between said first potential and said second electrode of said third transistor, said second node being connected directly to said second potential.

11. A semiconductor device according to claim 10, wherein R₄C₃=R₁C₂,

where R₄ is a resistance of said fourth resistor, C₃ and C₂ are capacitances of said third and second capacitors, respectively, and R₁ is a resistance of said first resistor.

12. A semiconductor device according to claim 10, wherein said second capacitor is a parasitic capacitor to said second electrode of said fourth transistor.

13. A constant current source circuit comprising:

a first transistor having a drain connected to a power supply line, and a gate and a source;

a second transistor having a drain connected to said power supply line, a gate connected to said gate of said first transistor and a source of said second transistor;

a third transistor having a drain connected directly to said source of said first transistor and a gate of said third transistor via a first node, and a source connected to a second node;

a fourth transistor having a drain connected directly to said source of said second transistor, a gate connected to said gate of said third transistor via said first node, and a source, said third and fourth transistors being operatively coupled to a first potential;

a first resistor connected between said source of said fourth transistor and a second node which is operatively coupled to a second potential; and

holding means for holding a potential difference between said gate and said source in each of said third and fourth transistors when said potential difference between said first potential and said second potential changes.

14. A constant current source circuit according to claim 13, wherein said holding means includes a second resistor connected between said second node and said second potential.

15. A constant current source circuit according to claim 14, wherein said holding means further includes a first capacitor connected between said second node and at least one of said first potential and said second potential.

16. A constant current source circuit according to claim 15, wherein a combination of said first capacitor and said second resistor functions as a low pass filter with a cut-off frequency of 1/{2π

R₂(C_(A)+Co)},

where R₂ is a resistance of said second resistor, C_(A) is a parasitic capacitance of said second node, and Co is a junction capacitance between a diffusion layer and a substrate on which said first to fourth transistors are formed.

17. A constant current source circuit according to claim 16, wherein said diffusion layer is formed to surround a region where said third and fourth transistors are formed.

18. A constant current source circuit according to claim 13, wherein said holding means includes:

a third resistor interposed between said source of said third transistor and said second node, said second node being connected directly to said second potential.

19. A constant current source circuit according to claim 13, wherein said holding means includes:

a fourth resistor interposed between said source of said third transistor and said second node;

a second capacitor connected between said first potential and said source of said fourth transistor; and

a third capacitor connected between said first potential and said source of said third transistor, said second node being connected directly to said second potential.

20. A constant current source circuit according to claim 19, wherein R₄C₃=R₁C₂,

where R₄ is a resistance of said fourth resistor, C₃ and C₂ are capacitances of said third and second capacitors, respectively, and R₁ is a resistance of said first resistor.

21. A constant current source circuit having a first power supply node, a second power supply node, and a ground node, said second power supply having a polarity opposite said first power supply, said circuit comprising:

a first transistor having a first electrode connected to said first power supply node;

a second transistor having a first electrode connected to said first power supply node;

a third transistor having a first electrode connected to a second electrode of said first transistor, said third transistor having at least one component connected to said second power supply node, thereby causing said third transistor to be operatively coupled to said second power supply node relative to said ground node;

a fourth transistor having a first electrode connected to a second electrode of said second transistor, said fourth transistor having at least one component connected to said second power supply node, thereby causing said fourth transistor to be operatively coupled to said second power supply node relative to said ground node; and

a low pass filter interconnected between said second power supply node, said ground potential node, and one electrode of at least one of said third transistor and said fourth transistor, said low pass filter thereby providing a noise immunity to said third transistor and said fourth transistor for voltage transients in at least one of said second power supply node and said ground node.