Sharing executable modules between user and kernel threads

• US 6,349,355 B1
• Filed: 02/06/1997
• Issued: 02/19/2002
• Est. Priority Date: 02/06/1997
• Status: Expired due to Term

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Cutshall, Scott, Odinak, Gilad, Draves, Richard P.
• Primary Examiner(s): Maung, Zarni
• Application Number:
  US08/795,591
• Time in Patent Office: 1,839 Days
• Field of Search: 711/6, 711/203-210, 711/213, 711/2, 711/202
• US Class Current: 711/6
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 12/1491 in a hierarchical protection system, e.g. privilege levels, memory rings
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system

Abstract

A computer system has a microprocessor that can execute in a non-privileged user mode and a privileged kernel mode. A user virtual address space is used when the microprocessor is in the user mode, and a kernel virtual address space is used when the microprocessor is in the kernel mode. Each of the address spaces has the same range of virtual addresses that is designated for shared components. The user virtual address space is mapped to an offset position within the kernel address space. When a user process calls a kernel function with a pointer argument, the pointer is biased before being dereferenced to account for the offset of the user address space within the kernel address space. This allows for sharing of position-dependent code, while still allowing the kernel to access the entire user address space.

Claims

1. In a computer system having privileged and non-privileged execution modes, a method comprising the following steps:

using at least a first virtual address space when in the non-privileged execution mode, wherein the first virtual address space includes a range of virtual addresses designated for shared components;

using at least a second virtual address space when in the privileged execution mode, wherein the second virtual address space also includes said range of virtual addresses designated for shared components;

mapping at least part of the first virtual address space to an offset position within the second virtual address space;

generating a memory reference to a virtual address in the first virtual address space;

biasing the memory reference to account for the offset position of the first virtual address space within the second virtual address space before dereferencing the memory reference in the privileged execution mode.

2. A method as recited in claim 1, wherein the mapping step comprises offsetting the first virtual address space by an address offset equal to the length of the range of virtual addresses designated for shared components.

3. A method as recited in claim 1, wherein the computer system has configurable memory segment offsets, at least a first memory segment offset being active in the privileged execution mode and at least a second memory segment being active in the non-privileged execution mode, respectively, the mapping step comprising:

assigning different values to the first and second memory segment offsets.

4. A method as recited in claim 1, wherein the computer system has configurable memory segment offsets, at least a first memory segment offset being active in the privileged execution mode and at least a second memory segment being active in the non-privileged execution mode, respectively, the mapping step comprising:

configuring the first and second memory segment offsets to have values that differ from each other by at least an amount equal to the length of the range of virtual addresses designated for shared components.

5. A method as recited in claim 1, wherein a process in the computer system has a plurality of virtual-to-physical address mappings, each identified by an address space identifier, the mapping step comprising:

assigning first and second address space identifiers to each process;

switching between the first and second address space identifiers of a particular process when switching between the non-privileged execution mode and the privileged execution mode.

6. A method as recited in claim 1, the mapping step comprising:

generating pairs of virtual-to-physical address mappings for each process, each pair including a first address mapping and a second address mapping;

switching between the first and second address mappings for a particular process when switching between the non-privileged execution mode and the privileged execution mode.

7. A method as recited in claim 1, the mapping step comprising:

assigning first and second address space identifiers to each process;

generating pairs of virtual-to-physical address mappings for each process, a first mapping of each pair being identified by the first address space identifier of the process, a second mapping of each pair being identified by the second address space identifier of the process;

switching between the first and second address space identifiers of the process when switching between the non-privileged execution mode and the privileged execution mode.

8. In a computer system having privileged and non-privileged execution modes, a method comprising the following steps:

using at least a first virtual address space when in the non-privileged execution mode, wherein the first virtual address space includes a range of virtual addresses designated for shared components;

using at least a second virtual address space when in the privileged execution mode, wherein the second virtual address space also includes said range of virtual addresses designated for shared components;

mapping at least part of the first virtual address space to an offset position within the second virtual address space;

generating a memory reference to a virtual address in the first virtual address space;

biasing the memory reference to account for the offset position of the first virtual address space within the second virtual address space before dereferencing the memory reference in the privileged execution mode;

loading position-dependent code configured to execute from a prescribed virtual address range within the range of virtual addresses designated for shared components;

mapping the prescribed virtual address range in the first virtual address space to the position-dependent code;

mapping the prescribed virtual address range in the second virtual address space to the position-dependent code;

invoking the position-dependent code in the first virtual address space from the non-privileged execution mode and in the second virtual address space from the privileged execution mode.

9. In a computer system having privileged and non-privileged execution modes, a method comprising the following steps:

using at least a first virtual address space when in the non-privileged execution mode, wherein the first virtual address space includes a range of virtual addresses designated for shared components;

using at least a second virtual address space when in the privileged execution mode, wherein the second virtual address space also includes said range of virtual addresses designated for shared components;

mapping at least part of the first virtual address space to an offset position within the second virtual address space;

generating a memory reference to a virtual address in the first virtual address space;

biasing the memory reference to account for the offset position of the first virtual address space within the second virtual address space before dereferencing the memory reference in the privileged execution mode;

loading a position-dependent program module configured to execute from a prescribed virtual address range within the range of virtual addresses designated for shared components;

mapping the prescribed virtual address range in the first virtual address space to the position-dependent program module as copy-on-write memory;

mapping the prescribed virtual address range in the second virtual address space to the position-dependent program module as copy-on-write memory;

sharing the position-dependent program module between a first execution thread executing in the non-privileged execution mode and a second execution thread executing in the privileged execution mode.

10. In a computer system having privileged and non-privileged execution modes, a method comprising the following steps:

executing a user process within a user virtual address space in the non-privileged execution mode;

designating a range of virtual addresses in the user virtual address space for shared components;

passing a memory reference to a system function from the user process, the system function executing within a system virtual address space in the privileged execution mode, the system virtual address space including said range of virtual addresses designated for shared components, the memory reference being to a location in the user virtual address space;

mapping at least part of the user virtual address space to an offset position within the system virtual address space;

biasing the memory reference to account for the offset position of the user virtual address space within the system virtual address space, the step of biasing being performed after passing the memory reference from the user process;

dereferencing the memory reference in the system function after biasing the memory reference.

11. A method as recited in claim 10, further comprising the following steps:

loading a position-dependent program module at a prescribed virtual address range within the range of virtual addresses designated for shared components;

sharing the position-dependent program module between the user process and the system function.

12. A method as recited in claim 10, wherein the computer system has configurable memory segment offsets, at least a first memory segment offset being active in the privileged execution mode and at least a second memory segment offset being active in the non-privileged execution mode, respectively, the mapping step comprising:

assigning different values to the first and second memory segment offsets.

13. A method as recited in claim 10, wherein the computer system has configurable memory segment offsets, at least a first memory segment offset being active in the privileged execution mode and at least a second memory segment offset being active in the non-privileged execution mode, respectively, the mapping step comprising:

configuring the first and second memory segment offsets to have values that differ from each other by at least an amount equal to the length of the range of virtual addresses designated for shared components.

14. A method as recited in claim 10, the mapping step comprising:

assigning first and second address space identifiers to the user process;

generating pairs of virtual-to-physical address mappings for the user process, a first mapping of each pair being identified by the first address space identifier, a second mapping of each pair being identified by the second address space identifier;

switching from the first address space identifier to the second address space identifier before executing the system function.

15. A method as recited in claim 10, the mapping step comprising:

generating pairs of virtual-to-physical address mappings for the user process, each pair including a first address mapping and a second address mapping;

switching from the first address mappings to the second address mappings before executing the system function.

16. In a computer system having privileged and non-privileged execution modes, a method comprising the following steps:

executing a user process within a user virtual address space in the non-privileged execution mode;

designating a range of virtual addresses in the user virtual address space for shared components;

passing a memory reference to a system function from the user process, the system function executing within a system virtual address space in the privileged execution mode, the system virtual address space including said range of virtual addresses designated for shared components, the memory reference being to a location in the user virtual address space;

mapping at least part of the user virtual address space to an offset position within the system virtual address space;

biasing the memory reference to account for the offset position of the user virtual address space within the system virtual address space, the step of biasing being performed after passing the memory reference from the user process;

dereferencing the memory reference in the system function after biasing the memory reference;

loading position-dependent code configured to execute from a prescribed virtual address range within the range of virtual addresses designated for shared components;

mapping the prescribed virtual address range in the user virtual address space to the position-dependent code;

mapping the prescribed virtual address range in the system virtual address space to the position-dependent code;

invoking the position-dependent code in the user virtual address space and in the system virtual address space.

17. A computer system comprising:

a processor having privileged and non-privileged execution modes;

a virtual memory system that defines a first virtual address space used by the processor in the privileged execution mode and a second virtual address space used by the processor in the non-privileged execution mode, the first and second virtual address spaces having a common range of virtual addresses designated for shared components;

wherein the virtual memory system maps at least part of the first virtual address space into the second virtual address space at an offset position within the second virtual address space;

a process that is executed by the processor, the process generating a memory reference to a virtual address in the first virtual address space, wherein the process provides the memory reference to a system function executing in the privileged execution mode;

wherein the virtual memory system biases the memory reference to account for the offset position of the first virtual address space within the second virtual address space before the system function dereferences the memory reference.

18. A computer system as recited in claim 17, further comprising:

a position-dependent program module configured to execute from a prescribed virtual address range within the range of virtual addresses designated for shared components;

at least parts of the position-dependent program module being mapped into both the first and second virtual address spaces at the prescribed virtual address range.

19. A computer system as recited in claim 17, wherein the processor has configurable memory segment offsets, at least a first memory segment offset being active in the privileged execution mode and at least a second memory segment being active in the non-privileged execution mode, respectively, the first and second memory segment offsets being having different values.

20. A computer system as recited in claim 17, wherein the processor has configurable memory segment offsets, at least a first memory segment offset being active in the privileged execution mode and at least a second memory segment being active in the non-privileged execution mode, respectively, the first and second memory segment offsets being configured to have values that differ from each other by at least an amount equal to the length of the range of virtual addresses designated for shared components.

21. A computer system as recited in claim 17, further comprising:

pairs of virtual-to-physical address mappings corresponding to the process, each pair including a first address mapping and a second address mapping;

wherein the virtual memory system switches between the first and second address mappings when switching between the non-privileged execution mode and the privileged execution mode.

22. A computer system as recited in claim 17, further comprising:

pairs of virtual-to-physical address mappings corresponding to the process, a first mapping of each pair being identified by a first address space identifier, a second mapping of each pair being identified by a second address space identifier;

wherein the virtual memory system switches between the first and second address space identifiers when switching between the non-privileged execution mode and the privileged execution mode.

23. In a computer system having privileged and non-privileged execution modes, a virtual memory system comprising:

a plurality of virtual-to-physical address mappings that define a first virtual address space used in the privileged execution mode and a second virtual address space used in the non-privileged execution mode, the first and second virtual address spaces having a common range of virtual addresses designated for shared components;

wherein the virtual-to-physical address mappings map at least part of the first virtual address space into the second virtual address space at an offset position within the second virtual address space.

24. A virtual memory system as recited in claim 23, further comprising configurable memory segment offsets, at least a first memory segment offset being active in the privileged execution mode and at least a second memory segment being active in the non-privileged execution mode, respectively, the first and second memory segment offsets having different values.

25. A virtual memory system as recited in claim 23, further comprising configurable memory segment offsets, at least a first memory segment offset being active in the privileged execution mode and at least a second memory segment being active in the non-privileged execution mode, respectively, the first and second memory segment offsets having values that differ from each other by at least an amount equal to the length of the range of virtual addresses designated for shared components.

26. A virtual memory system as recited in claim 23, further comprising:

pairs of virtual-to-physical address mappings corresponding to a particular process, each pair including a first address mapping and a second address mapping;

the first address mappings being used in the non-privileged execution mode, the second address mappings being used in the privileged execution mode.

27. A virtual memory system as recited in claim 23, further comprising:

pairs of virtual-to-physical address mappings corresponding to a particular process, a first mapping of each pair being identified by a first address space identifier, a second mapping of each pair being identified by a second address space identifier;

the first address space identifier being used in the non-privileged execution mode, the second address space identifier being used in the privileged execution mode.

28. A computer-readable medium having instructions for performing steps in conjunction with a computer having privileged and non-privileged execution modes, the steps comprising:

using at least a first virtual address space when in the non-privileged execution mode, wherein the first virtual address space includes a range of virtual addresses designated for shared components;

using at least a second virtual address space when in the privileged execution mode, wherein the second virtual address space also includes said range of virtual addresses designated for shared components;

mapping at least part of the first virtual address space to an offset position within the second virtual address space;

generating a memory reference to a virtual address in the first virtual address space;

biasing the memory reference to account for the offset position of the first virtual address space within the second virtual address space before dereferencing the memory reference in the privileged execution mode.

29. A computer-readable medium as recited in claim 28, wherein the mapping step comprises offsetting the first virtual address space by an address offset equal to the length of the range of virtual addresses designated for shared components.

30. A computer-readable medium as recited in claim 28, wherein the computer system has configurable memory segment offsets, at least a first memory segment offset being active in the privileged execution mode and at least a second memory segment being active in the non-privileged execution mode, respectively, the mapping step comprising:

assigning different values to the first and second memory segment offsets.

31. A computer-readable medium as recited in claim 28, wherein the computer system has configurable memory segment offsets, at least a first memory segment offset being active in the privileged execution mode and at least a second memory segment being active in the non-privileged execution mode, respectively, the mapping step comprising:

configuring the first and second memory segment offsets to have values that differ from each other by at least an amount equal to the length of the range of virtual addresses designated for shared components.

32. A computer-readable medium as recited in claim 28, wherein a process in the computer system has a plurality of virtual-to-physical address mappings, each identified by an address space identifier, the mapping step comprising:

assigning a first and second address space identifier to each process;

switching between the first and second address space identifiers of a particular process when switching between the non-privileged execution mode and the privileged execution mode.

33. A computer-readable medium as recited in claim 28, the mapping step comprising:

assigning first and second address space identifiers to each process;

generating pairs of virtual-to-physical address mappings for each process, a first mapping of each pair being identified by the first address space identifier for the process, a second mapping of each pair being identified by the second address space identifier for the process;

switching between the first and second address space identifiers of the process when switching between the non-privileged execution mode and the privileged execution mode.

34. A computer-readable medium as recited in claim 28, the mapping step comprising:

generating pairs of virtual-to-physical address mappings for each process, each pair including a first address mapping and a second address mapping;

switching between the first and second address mappings of a particular process when switching between the non-privileged execution mode and the privileged execution mode.

35. A computer-readable medium having instructions for performing steps in conjunction with a computer having privileged and non-privileged execution modes, the steps comprising:

using at least a first virtual address space when in the non-privileged execution mode, wherein the first virtual address space includes a range of virtual addresses designated for shared components;

using at least a second virtual address space when in the privileged execution mode, wherein the second virtual address space also includes said range of virtual addresses designated for shared components;

mapping at least part of the first virtual address space to an offset position within the second virtual address space;

generating a memory reference to a virtual address in the first virtual address space;

biasing the memory reference to account for the offset position of the first virtual address space within the second virtual address space before dereferencing the memory reference in the privileged execution mode;

loading position-dependent code configured to execute from a prescribed virtual address range within the range of virtual addresses designated for shared components;

mapping the prescribed virtual address range in the first virtual address space to the position-dependent code;

mapping the prescribed virtual address range in the second virtual address space to the position-dependent code;

invoking the position-dependent code in the first virtual address space from the non-privileged execution mode and in the second virtual address space from the privileged execution mode.

36. A computer-readable medium having instructions for performing steps in conjunction with a computer having privileged and non-privileged execution modes, the steps comprising:

using at least a first virtual address space when in the non-privileged execution mode, wherein the first virtual address space includes a range of virtual addresses designated for shared components;

using at least a second virtual address space when in the privileged execution mode, wherein the second virtual address space also includes said range of virtual addresses designated for shared components;

mapping at least part of the first virtual address space to an offset position within the second virtual address space;

generating a memory reference to a virtual address in the first virtual address space;

biasing the memory reference to account for the offset position of the first virtual address space within the second virtual address space before dereferencing the memory reference in the privileged execution mode;

loading a position-dependent program module configured to execute from a prescribed virtual address range within the range of virtual addresses designated for shared components;

mapping the prescribed virtual address range in the first virtual address space to the position-dependent program module as copy-on-write memory;

mapping the prescribed virtual address range in the second virtual address space to the position-dependent program modules as copy-on-write memory;

sharing the position-dependent program module between a first execution thread executing in the non-privileged execution mode and a second execution thread executing in the privileged execution mode.