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User-prioritized cache replacement

  • US 6,349,365 B1
  • Filed: 10/08/1999
  • Issued: 02/19/2002
  • Est. Priority Date: 10/08/1999
  • Status: Expired due to Term
First Claim
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1. A microprocessor comprising:

  • a cache comprising a plurality of cache line storage locations and a corresponding plurality of replacement priority storage locations;

    a predecode unit, wherein the predecode unit is configured to receive and predecode instruction bytes, wherein the predecode unit is further configured to detect replacement priority information embedded within the instruction bytes and convey the replacement priority information with the predecoded instruction bytes to the cache for storage in the replacement priority storage locations and cache line storage locations, respectively; and

    a cache controller coupled to the cache and configured to use the contents of the replacement priority storage locations to determine which of the cache line storage locations to overwrite.

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