User-prioritized cache replacement
First Claim
1. A microprocessor comprising:
- a cache comprising a plurality of cache line storage locations and a corresponding plurality of replacement priority storage locations;
a predecode unit, wherein the predecode unit is configured to receive and predecode instruction bytes, wherein the predecode unit is further configured to detect replacement priority information embedded within the instruction bytes and convey the replacement priority information with the predecoded instruction bytes to the cache for storage in the replacement priority storage locations and cache line storage locations, respectively; and
a cache controller coupled to the cache and configured to use the contents of the replacement priority storage locations to determine which of the cache line storage locations to overwrite.
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Accused Products
Abstract
A method and apparatus for encoding cache replacement priority information is disclosed. A computer software program may be used to allow programmers to specify which portions of source or object code being generated should be treated as high priority with respect to cache line replacement. The cache line replacement information may be encoded as special prefix bits/bytes, special opcodes, or as a separate data file. The software program may also be configured to autonomously determine which portions of the object code being generated should be identified as high priority with respect to cache line replacement. The program may also allow the programmer to specify certain points in the code after which instructions that had previously been identified as high priority should be reclassified as low priority. Opcodes or prefix bytes clearing previously stored cache replacement information may also be encoded in the object code. A microprocessor and computer system configured to execute code with embedded cache line replacement information are also disclosed.
74 Citations
27 Claims
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1. A microprocessor comprising:
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a cache comprising a plurality of cache line storage locations and a corresponding plurality of replacement priority storage locations;
a predecode unit, wherein the predecode unit is configured to receive and predecode instruction bytes, wherein the predecode unit is further configured to detect replacement priority information embedded within the instruction bytes and convey the replacement priority information with the predecoded instruction bytes to the cache for storage in the replacement priority storage locations and cache line storage locations, respectively; and
a cache controller coupled to the cache and configured to use the contents of the replacement priority storage locations to determine which of the cache line storage locations to overwrite. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A computer software program embodied on a computer-readable medium, wherein the computer software program comprises a plurality of instructions, wherein the plurality of instructions are configured to compile source code into object code, wherein compiling the source code comprises:
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translating source code instructions into object code instructions;
determining which source code instructions are high priority for caching; and
encoding cache priority information corresponding to the tags into the object code. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A computer software program embodied on a computer-readable medium, wherein the computer software program comprises a plurality of instructions, wherein the plurality of instructions are configured to:
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monitor the execution of an object code application, determine which portions of the object code are executed more frequently than the object code in general; and
encode cache priority information for at least the more frequently executed portions. - View Dependent Claims (24, 25, 26, 27)
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Specification