System for executing instructions having flag for indicating direct or indirect specification of a length of operand data

• US 6,349,379 B2
• Filed: 02/18/1998
• Issued: 02/19/2002
• Est. Priority Date: 04/30/1997
• Status: Expired due to Term

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Amies, Christopher, Long, Timothy Merrick, Gibson, Ian
• Primary Examiner(s): Ellis, Richard L.
• Application Number:
  US09/025,194
• Publication Number:
  US 20010021971A1
• Time in Patent Office: 1,462 Days
• Field of Search: 712/210, 712/225
• US Class Current: 712/210
• CPC Class Codes: G06F 17/147 Discrete orthonormal transforms, e.g. discrete cosine transform, discrete sine transform, and variations therefrom, e.g. modified discrete cosine transform, integer transforms approximating the discrete cosine transform G06F17/145 takes precedence
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3897 with adaptable data path
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 2200/28 involving image processing hardware
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/90 using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals

Abstract

The present invention discloses an image processor (224) for executing a computer instruction set (280, 290) in the form of an opcode (281), at least one operand (283-285) which is, or indicates the location of data to be processed. The data to be processed consists of a variable length stream of data and each instruction includes a length field (297) containing data specifying the number of items of data to be processed or, if that number exceeds the size of the length field, a predetermined location of a previously allocated storage area at which that number is stored.

Claims

1. A graphics processor for executing a computer instruction set comprising a plurality of instructions each of which has an instruction opcode and at least one operand, wherein a length of all the instructions is equal and of a like predetermined length, the opcode corresponds to a type of calculation to be performed on the operand(s), each operand is data to be processed in the calculation or specifies an address of the data, a result of the calculation represents processed image data, and each instruction includes a length field that includes data specifying a number of items of data to be processed or, if the number exceeds a size of the length field, a predetermined location of a previously-allocated storage area at which the number is stored, and a flag indicating whether the number is stored in the storage area or the length field, whereby said processor for each instruction processes a corresponding number of data items to thereby facilitate processing of variable-length streams of data.

2. A processor as claimed in claim 1, wherein a time required to process the corresponding number of data items exceeds a time to fetch and decode each instruction.

3. A processor as claimed in claim 1, wherein a number of operands per instruction is selected from a range of integers between one and four.

4. A graphics processor for executing a computer instruction set comprising a plurality of instructions each of which has an instruction opcode and at least one operand, wherein a length of all of the instructions is equal and of a like predetermined length, the opcode corresponds to a type of calculation to be performed on the operand(s), each operand is data to be processed in the calculation or specifies an address of the data, a result of the calculation represents processed image data, and each instruction includes a length field containing data specifying a number of items of data to be processed or, if the number exceeds a size of the length field, a predetermined location of a previously-allocated storage area at which the number is stored, whereby said processor for each instruction processes a corresponding number of data items to thereby facilitate processing of variable-length streams of data.

5. A method of executing a computer instruction, wherein the computer instruction includes an instruction opcode and at least one operand, the opcode corresponds to a type of calculation to be performed on the at least one operand, each operand is data to be processed in the calculation or specifies an address of the data, and a result of the calculation represents processed image data, said method comprising the steps of:

determining a number of items to be processed by the instruction, wherein the instruction includes a length field that includes data specifying the number of items of data to be processed or, if the number exceeds a size of the length field, a predetermined location of a previously-allocated storage area at which the number is stored, and a flag indicating whether the number is stored in the storage area or the length field; and

processing the number of data items by the instruction to thereby facilitate processing of variable-length streams of data.

6. An apparatus for executing a computer instruction, wherein the computer instruction includes an instruction opcode and at least one operand, the opcode corresponds to a type of calculation to be performed on the at least one operand, each operand is data to be processed in the calculation or specifies an address of the data, and a result of the calculation represents processed image data, said apparatus comprising:

a determination circuit adapted to determine a number of items to be processed by the instruction, wherein the instruction includes a length field that includes data specifying the number of items of data to be processed or, if the number exceeds a size of the length field, a predetermined location of a previously-allocated storage area at which the number is stored, and a flag indicating whether the number is stored in the storage area or the length field; and

a processor circuit adapted to process the number of data items by the instruction to thereby facilitate processing of variable-length streams of data.

7. A computer-readable medium storing a computer program for executing a computer instruction, wherein the computer instruction including an instruction opcode and at least one operand, the opcode corresponds to a type of calculation to be performed on the at least one operand, each operand is data to be processed in the calculation or specifies an address of the data, and a result of the calculation represents processed image data, the computer program comprising:

code for determining a number of items to be processed by the instruction, wherein the instruction includes a length field that includes data specifying the number of items of data to be processed or, if the number exceeds a size of the length field, a predetermined location of a previously-allocated storage area at which the number is stored, and a flag indicating whether the number is stored in the storage area or the length field; and

code for processing the number of data items by the instruction to thereby facilitate processing of variable-length streams of data.