Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessor

• US 6,349,380 B1
• Filed: 03/12/1999
• Issued: 02/19/2002
• Est. Priority Date: 03/12/1999
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shahidzadeh, Shahrokh, Bigbee, Bryant E., Colwell, Robert P., Papworth, David B., Binns, Frank
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US09/267,796
• Time in Patent Office: 1,075 Days
• Field of Search: 712/1, 712/41, 712/43, 712/200, 712/208, 712/209, 712/211, 712/113, 711/1, 711/2, 711/5, 711/202, 711/203, 711/206, 711/207, 711/208, 711/209, 711/211, 711/212, 711/220, 711/205, 711/201, 711/204, 711/215, 711/221, 711/213, 711/216, 711/214
• US Class Current: 712/211
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 9/342 Extension of operand address space

Abstract

A microprocessor for providing an extended linear address of more than 32 bits. The extended linear address may be provided by concatenating a linear address with a segment selector extension, or by concatenating the values from two registers. Hierarchical translation of a linear address to a physical address is performed in which the number of levels in the hierarchy depends upon whether the linear address is an extended linear address.

Claims

1. A microprocessor having an extended linear address mode, the microprocessor comprising:

a decoder to decode instructions so as to provide an offset;

a segment register to store a segment selector and a segment extension; and

an address generation unit to generate an extended linear address, wherein the extended linear address comprises the offset, the segment selector, and the segment extension;

wherein during a page walk to translate the extended linear address to a physical address while in the extended linear address mode, the microprocessor utilizes a first pointer to reference a first table as a page directory; and

while not in the extended linear address mode during the page walk the microprocessor utilizes a second pointer to reference a second table as the page directory.

2. The microprocessor as set forth in claim 1, wherein the extended linear address comprises a lower portion and an upper portion, wherein the address generation unit provides the lower portion as the sum of the offset and a base address, wherein the base address is provided by a segment descriptor from a descriptor table stored in memory and pointed to by the segment selector, wherein the upper portion is equal to the segment extension.

3. The microprocessor as set forth in claim 2, wherein the microprocessor is a 32 bit processor and the extended linear address has more than 32 bits.

4. The microprocessor as set forth in claim 1, wherein at least a portion of the segment extension stored in the segment register is used as an offset to point to an entry in a table, wherein the entry comprises the first pointer, wherein the second pointer is not a function of any portion of the segment extension.

5. A computer comprising:

a system bus;

memory coupled to the system bus; and

a microprocessor coupled to the system bus, the microprocessor comprising

a decoder to decode instructions so as to provide an offset;

a segment register to store a segment selector and a segment extension; and

an address generation unit to generate an extended linear address, wherein the extended linear address comprises the offset, the segment selector, and the segment extension;

wherein during a page walk to translate the extended linear address to a physical address while in the extended linear address mode, the microprocessor utilizes a first pointer to reference a first table as a page directory; and

while not in the extended linear address mode during the page walk the microprocessor utilizes a second pointer to reference a second table as the page directory.

6. The computer as set forth in claim 5, wherein the extended linear address comprises a lower portion and an upper portion, wherein the address generation unit provides the lower portion as the sum of the offset and a base address, wherein the base address is provided by a segment descriptor from a descriptor table stored in the memory and pointed to by the segment selector, wherein the upper portion is equal to the segment extension.

7. The computer as set forth in claim 5, wherein the microprocessor is a 32 bit processor and the extended linear address has more than 32 bits.

8. The microprocessor as set forth in claim 5, wherein at least a portion of the segment extension stored in the segment register is used as an offset to point to an entry in a table, wherein the entry comprises the first pointer, wherein the second pointer is not a function of any portion of the segment extension.

9. A microprocessor having an extended linear address mode, the microprocessor comprising:

a register file;

a decoder to decode instructions belonging to an instruction set, wherein the instruction set includes an instruction to specify an extended linear address, wherein the instruction to specify an extended linear address names a first source register in the register file and a second source register in the register file; and

an address generation unit to generate an extended linear address as a concatenation of values stored in the first and second source registers;

wherein during a page walk to translate the extended linear address to a physical address while in the extended linear address mode, the microprocessor utilizes a first pointer to reference a first table as a page directory; and

while not in the extended linear address mode during the page walk the microprocessor utilizes a second pointer to reference a second table as the page directory.

10. The microprocessor as set forth in claim 9, wherein the microprocessor is a 32 bit processor and the extended linear address has more than 32 bits.

11. The computer system as set forth in claim 9 wherein at least a portion of the segment extension stored in the segment register is used as an offset to point to an entry in a table, wherein the entry comprises the first pointer, wherein the second pointer is not a function of any portion of the segment extension.

14. The computer system as set forth in claim 9, wherein at least a portion of the segment extension stored in the segment register is used as an offset to point to an entry in a table, wherein the entry comprises the first pointer, wherein the second pointer is not a function of any portion of the segment extension.

12. A computer comprising:

a system bus;

memory coupled to the system bus; and

a microprocessor coupled to the system bus, the microprocessor having an extended linear address mode, the microprocessor comprising

a register file;

a decoder to decode instructions belonging to an instruction set, wherein the instruction set includes an instruction to specify an extended linear address, wherein the instruction to specify an extended linear address names a first source register in the register file and a second source register in the register file; and

an address generation unit to generate an extended linear address as a concatenation of values stored in the first and second source registers;

wherein during a page walk to translate the extended linear address to a physical address while in the extended linear address mode, the microprocessor utilizes a first pointer to reference a first table as a page directory; and

while not in the extended linear address mode during the page walk the microprocessor utilizes a second pointer to reference a second table as the page directory.

13. The computer as set forth in claim 12, wherein the microprocessor is a 32 bit processor and the extended linear address has more than 32 bits.

15. A method to perform a page walk, the method comprising:

selecting a first pointer to point to a first table in memory when in an extended linear address mode; and

selecting a second pointer to point to a second table in memory when not in the extended linear address mode;

wherein the first table serves as a page directory when in the extended linear address mode and the second table serves as the page directory when not in the extended linear address mode.

16. The method as set forth in claim 15, wherein the first pointer is obtained as an offset into a table, wherein the offset is provided by at least a portion of a segment extension stored in a segment register, wherein the second pointer is not a function of any portion of the segment extension.

17. An article of manufacture comprising a computer readable memory, wherein stored in the computer readable memory are instructions that when executed by a computer cause the computer to:

select a first pointer to point to a first table in memory when the computer is in an extended linear address mode; and

select a second pointer to point to a second table in memory when the computer is not in the extended linear address mode;

wherein the first table serves as a page directory when in the extended linear address mode and the second table serves as the page directory when not in the extended linear address mode.

18. The article of manufacture as set forth in claim 17, wherein the first pointer is obtained as an offset into a table, wherein the offset is provided by at least a portion of a segment extension stored in a segment register, wherein the second pointer is not a function of any portion of the segment extension.