Performance monitoring in a NUMA computer

• US 6,349,394 B1
• Filed: 03/31/1999
• Issued: 02/19/2002
• Est. Priority Date: 03/31/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Glasco, David Brian, Rajamony, Ramakrishnan, Rawson, Freeman Leigh III, Elnozahy, Elmootazbellah Nabil, Chiprout, Eli, Brock, Bishop Chapman, Rockhold, Ronald Lynn
• Primary Examiner(s): Iqbal, Nadeem
• Application Number:
  US09/282,626
• Time in Patent Office: 1,056 Days
• Field of Search: 714/47, 714/48, 714/52, 714/4, 714/25, 714/26, 714/37, 714/39, 714/41, 714/43, 709/203, 709/249, 709/250
• US Class Current: 714/47.2
• CPC Class Codes: G06F 11/302 where the computing system component is a software system
• CPC Class Codes: G06F 11/3072 where the reporting involves data filtering, e.g. pattern matching, time or event triggered, adaptive or policy-based reporting
• CPC Class Codes: G06F 11/3471 Address tracing
• CPC Class Codes: G06F 11/349 for interfaces, buses
• CPC Class Codes: G06F 2201/87 Monitoring of transactions
• CPC Class Codes: G06F 2201/88 Monitoring involving counting

Abstract

A performance monitor for a computer system that includes an interface, a filter module, and an address mapping module. The interface is suitable for coupling to an interconnect network of the computer system. The interconnect network links a local node of the system with at least one remote node of the system. The interface is configured to extract physical address information from a transaction traversing the interconnect network. The filter module associates the physical address with one of several memory blocks, where each memory block comprises a contiguous portion of the system'"'"'s physical address space. The address mapping module associates the identified memory block with at least one range of virtual addresses associated with at least one of a plurality of concurrently executing programs and increments each of a set of access counters. The association between the selected memory block and the access counters is facilitated by a pointer field corresponding to the memory block.

Claims

1. A performance monitor, comprising:

an interface suitable for coupling to an interconnect network of a computer system, the interconnect network linking a local node of the computer with at least one remote node of the computer system, wherein the interface unit is configured to extract a physical address information a transaction traversing the interconnect network;

a filter module adapted for associating the physical address with one of a plurality of memory blocks; and

an address mapping module configured to associate the memory block with at least one of a plurality of concurrently executing programs and, responsive thereto, incrementing at least one of a plurality of corresponding access counters.

2. The performance monitor of claim 1, wherein the interface unit is configurable to selectively monitor transactions either incoming to or outgoing from the local node.

3. The performance monitor of claim 1, wherein the filter module includes a plurality of region filters adapted to receive pertinent transaction information including physical address information and further wherein an output of each of the filters is indicative of whether the pertinent information including the physical address information matches a set of predetermined criteria.

4. The performance monitor of claim 3, wherein each of the regions and the predetermined criteria are defined by a corresponding region filter wherein the region filter is programmably alterable via a programming interface coupled to an I/O bus of the local node.

5. The performance monitor of claim 3, wherein each of the region filters is associated with a contiguous region of physical address space and wherein each of the regions is comprised of at least one of the plurality of memory blocks and further wherein the size and number of memory blocks comprising each of the regions is programmably defined by the region descriptor.

6. The performance monitor of claim 1, wherein each of the memory blocks is associated with a corresponding block counter, and wherein the filter module is adapted to increment the block counter if the physical address is within the block counter'"'"'s corresponding memory block.

7. The performance monitor of claim 1, wherein the mapping module interprets a pointer field corresponding to each of the memory blocks, wherein the pointer field is indicative of which of the plurality of concurrently executing programs is associated with the memory block.

8. The performance monitor of claim 1, further comprising an interrupt unit adapted to issue an interrupt if any of the access counters exceeds a specified value.

9. The performance monitor of claim 1, wherein the interface unit is configurable to detect a node ID information and to monitor the transaction only if the node ID matches one of a programmable set of node IDs.

10. The performance monitor of claim 1, wherein the interface unit is configurable to detect transaction type information and to monitor the transaction only if the transaction type matches one of a programmable set of transaction types.

11. A computer system, comprising:

a local node including at least one processor coupled to a local memory of the local node via a local bus of the local node;

at least one remote node, each of the remote nodes including at least one processor coupled to a local memory of the corresponding remote node via a local bus of the remote node;

an interconnect network coupling the remote node to the local node and via which the processor of the local node can access the local memory of the remote node and via which the processor of the remote node can access the local memory of the local node; and

a performance monitor including an interface coupled to the interconnect network and configured to extract physical address information from a transaction traversing the interconnect network, a filter module adapted for associating the physical address with one of a plurality of memory blocks, and a mapping module configured to associate the selected memory block with at least one of a plurality of concurrently executing programs and, responsive thereto, incrementing at least one of a plurality of corresponding access counters.

12. The computer system of claim 11, wherein the filter module includes a plurality of region filters adapted to receive the physical address, wherein each of the region filters is associated with a contiguous region of physical address space and further wherein an output signal of each of the filters is indicative of whether the physical address lies within the corresponding region.

13. The computer system of claim 12, wherein each of the regions is defined by a corresponding region descriptor including a base address field wherein the plurality of regions descriptors is programmably alterable via a programming interface coupled to an I/O bus of the local node.

14. The computer system of claim 12, wherein each of the regions of physical address space comprises at least one of the memory blocks.

15. The computer system of claim 14, wherein the number and size of the memory blocks comprising each of the regions is programmably alterable via the programming interface.

16. A method of monitoring performance of a computer system comprising:

defining physical address boundaries for a plurality of memory blocks;

concurrently executing a plurality of programs on a computer system comprising a local node and at least one remote node coupled to the local node via an interconnect network;

extracting physical address information from transactions traversing the interconnect network and associating the physical address with one of the plurality of memory blocks;

associating the selected memory block with at least one of a set of virtual address ranges associated with at least one of a plurality of programs, and;

incrementing access counters corresponding to each of the virtual address ranges.

17. The method of claim 16, wherein the step of defining the memory blocks comprises defining boundaries for a plurality of physical address regions and further defining a number and size of memory blocks within each of the plurality of physical address regions.

18. The method of claim 16, further comprising selecting either incoming or outgoing transactions for monitoring.

19. The method of claim 16, wherein the step of associating the selected memory block with the virtual address ranges includes interpreting a pointer field corresponding to the memory blocks.

20. The method of claim 16, further comprising interrupting the computer system if any of the access counters exceeds a programmable maximum value.