Method and apparatus for generating expect data from a captured bit pattern, and memory device using same

• US 6,349,399 B1
• Filed: 09/03/1998
• Issued: 02/19/2002
• Est. Priority Date: 09/03/1998
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A.
• Primary Examiner(s): Ton, David
• Application Number:
  US09/146,860
• Time in Patent Office: 1,265 Days
• Field of Search: 370/247, 370/242, 714/744, 714/738, 714/739, 327/41
• US Class Current: 714/744
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of these applied data signals have been properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated from the captured first group of applied data signals. A second group of the applied data signals are then captured after the first group. The second group of applied data signals are determined to have been properly captured when the second captured group of applied data signals corresponds to the group of expect data signals. In this way, when capture of the applied series of data signals is shifted in time from an expected initial capture point, subsequent captured groups of applied data signals are compared to their correct expected data signals in order to determine whether that group, although shifted in time, was nonetheless correctly captured. A pattern generator generates expect data signals in this manner, and this pattern generator may be utilized in a synchronization circuit to synchronize a plurality of clock signals. This pattern generator is suitable for use in synchronization circuits and a variety of integrated circuits, but is particularly well-suited for synchronizing command and data clocks applied to SLDRAMs.

Claims

1. A method for generating expect digital signals for a series of applied digital signals having a known sequence to determine if applied digital signals are being properly captured, comprising:

capturing a first group of the applied digital signals;

generating a group of expect digital signals from the captured first group of applied digital signals;

capturing a second group of the applied digital signals after the first group; and

determining the second group of applied digital signals was properly captured when the second captured group of applied digital signals corresponds to the generated group of expect digital signals.

2. The method of claim 1 wherein the series of applied digital signals comprises a 15 bit pseudo-random bit sequence of digital signals.

3. The method of claim 2 wherein the 15 bit pseudo-random bit sequence comprises the repeating bit sequence of “

111101011001000.”

4. The method of claim 1 wherein each group comprises four data signals.

5. The method of claim 1 wherein each group of applied digital signals includes four digital signals, and generating the group of expect digital signals comprises:

storing the four digital signals of the first group on respective first through fourth output nodes;

developing a first logic signal from the signal on the four output nodes;

developing a second logic signal from three of the four signals on the four output nodes;

coupling either the digital signal on the first output node or the complement of this digital signal to a first storage node responsive to the first logic signal to develop a first expect digital signal on the first storage node;

coupling either the digital signal on the second output node or the complement of this digital signal to a second storage node responsive to the second logic signal to develop the second expect data signal on the second storage node;

coupling either the data signal on the third output node or the complement of this data signal to a third storage node responsive to the data signal on the first output node and the data signal on the fourth output node to develop the third expect data signal on the third storage node;

coupling either the data signal on the fourth output node or the complement of this data signal to a fourth storage node responsive to the data signal on the first output node to develop the fourth expect data signal on the fourth storage node; and

coupling the first through fourth storage nodes to the first through fourth output nodes, respectively, to apply the four expect data signals on these respective nodes.

6. A method for synchronizing a clock signal applied on a clock terminal of an SLDRAM, comprising:

placing the SLDRAM in a synchronization mode;

applying the clock signal;

generating an internal clock signal responsive to the external clock signal, the internal clock signal having a phase relative to the external clock signal;

applying a repeating sequence of digital signals on each of a plurality of data terminals of the SLDRAM, each sequence having a known pattern;

capturing a group of digital signals on each of the data terminals responsive to the internal clock signal;

generating a series of expect data groups, each expect data group including a plurality of expect digital signals having values determined in response to the values of expect digital signals in the preceding expect data group, and the values of the digital signals in the first expect data group being determined responsive to digital signals from one of the captured groups of digital signals;

capturing a subsequent group of digital signals applied on the data terminals responsive to the internal clock signal;

comparing the digital signals in the subsequent group to the expect digital signals in the corresponding expect data group, and determining the subsequent group was successfully captured when each of the digital signals the subsequent group has its expected value;

storing the results of this comparison;

adjusting the phase of the clock signal;

repeating the acts of capturing a subsequent group of digital signals through adjusting the phase of the internal clock signal until a predetermined number of phases have been utilized for the internal clock signal; and

selecting a phase of the internal clock signal from one of stored phases that successfully captured the applied digital signals.

7. The method of claim 6 wherein applying a repeating sequence of digital signals on each of a plurality of data terminals comprises applying a true repeating 15 bit pseudo-random bit sequence on every other data terminal and applying the complement of this true sequence on those data terminals not receiving the true sequence.

8. The method of claim 6 wherein each group comprises four digital signals.

9. The method of claim 6 wherein the digital signals from one of the captured groups of digital signals used to determine the digital signals in the first expect data group comprise four captured digital signals applied sequentially on a FLAG terminal of the SLDRAM.

10. The method of claim 6 wherein comparing the digital signals comprises comparing the digital signals in a predetermined number of subsequent groups to their corresponding expect digital signals for each phase of the internal clock signal, and determining captures for a respective phase were successful only when the digital signals in all subsequent groups have their corresponding expected values.

11. A method of adaptively adjusting the phase of an internal clock signal relative to an external clock signal, the internal clock signal triggering a latch to store a digital signal, the method comprising:

repetitively applying digital signals to the latch in a known repeating sequence;

storing a first group of digital signals in the latch responsive to the internal clock signal having a first phase;

generating expected values for a next group of digital signals to be stored in the latch responsive to the stored first group of digital signals;

storing a second group of digital signals in the latch responsive to the internal clock signal having the first phase;

comparing the digital signals of the second group to their expected values to determine if the stored digital signals were successfully captured by the latch, and storing the results of this comparison;

repeating the acts of repetitively applying digital signals to comparing the digital signals for a plurality of phases of the internal clock signal; and

selecting a phase of the clock signal that caused the latch to store digital signals having the expected values.

12. The method of claim 11 wherein repetitively applying digital signals comprises applying a repeating 15 bit pseudo-random bit sequence of digital signals.

13. The method of claim 12 wherein the 15 bit pseudo-random bit sequence comprises the repeating bit sequence of “

111101011001000.”

14. The method of claim 11 wherein each group comprises four digital signals.

15. The method of claim 11 wherein generating the expected values for a next group of digital signals to be stored in the latch responsive to the stored first group of digital signals and storing a second group of digital signals in the latch responsive to the internal clock signal having the first phase are performed at the same time.

16. A method of adaptively adjusting the phase of an internal clock signal relative to an external clock signal, the internal clock signal triggering a latch to store a digital signal, the method comprising:

repetitively applying digital signals to the latch in a known repeating sequence;

storing a first group of digital signals in the latch responsive to the internal clock signal having a first phase;

generating an expect group of digital signals in response to the values of the stored first group of digital signals;

storing a next group of digital signals in the latch responsive to the internal clock signal having the first phase;

comparing the digital signals of the next group to their expected values to determine if the stored digital signals were successfully captured by the latch, and storing the results of this comparison;

adjusting the phase of the internal clock signal;

generating a next expect group of digital signals in response to the values of the current expect group of digital signals;

storing a next group of digital signals in the latch responsive to the internal clock signal having the adjusted phase;

comparing the digital signals of the next group to their expected values to determine if the stored digital signals were successfully captured by the latch, and storing the results of this comparison;

repeating adjusting the phase of the internal clock signal to comparing the digital signals of the next group for a plurality of phases of the internal clock signal; and

selecting a phase of the internal clock signal that caused the latch to store digital signals having the expected values.

17. The method of claim 16 wherein generating a next expect group of digital signals occurs sequentially responsive to the next group of digital signals being stored in the latch.

18. The method of claim 16 wherein repetitively applying digital signals comprises applying a repeating 15 bit pseudo-random bit sequence of digital signals.

19. The method of claim 18 wherein the 15 bit pseudo-random bit sequence comprises the repeating bit sequence of “

111101011001000.”