Method of producing multilayer circuit board

• US 6,350,365 B1
• Filed: 08/09/2000
• Issued: 02/26/2002
• Est. Priority Date: 08/12/1999
• Status: Expired due to Fees

• Current Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Original Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Inventors: Koyama, Toshinori, Katagiri, Noritaka
• Primary Examiner(s): Phasge, Arun S.
• Application Number:
  US09/634,783
• Time in Patent Office: 566 Days
• Field of Search: 205/125, 205/162, 205/163, 205/165, 205/167, 205/169
• US Class Current: 205/125
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 2201/0347 Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
• CPC Class Codes: H05K 2201/09481 Via in pad; Pad over filled via
• CPC Class Codes: H05K 2201/09509 Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/09536 Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• CPC Class Codes: H05K 2201/09563 Metal filled via
• CPC Class Codes: H05K 2201/0959 Plated through-holes or plated blind vias filled with insulating material
• CPC Class Codes: H05K 2201/096 Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 3/28 Applying non-metallic protective coatings H05K3/0091 takes precedence; methods for intermediate insulating layers for build-up multilayer circuits H05K3/4673
• CPC Class Codes: H05K 3/426 initial plating of through-holes in substrates without metal
• CPC Class Codes: H05K 3/4602 characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Abstract

A method of producing a multilayer circuit board comprising a core substrate and a plurality of layers of wiring lines on both sides of the core substrate with an insulation layer being interposed therebetween; the layers of wiring lines on both sides being interconnected by conducting members provided on the inside walls of through holes going through the core substrate, and the interposed insulation layer. The method further comprising, wiring lines with an upper layer of wiring lines wherein the conducting member on the inside wall of the through hole and the via are formed in separate steps. The method can provide a multilayer circuit board which can advantageously be used to mount a chip or device thereon having an increased number of electrodes or terminals.

Claims

1. A method of producing a multilayer circuit board which comprises a core substrate and a plurality of layers of wiring lines on both sides of the core substrate, the layers of wiring lines being on each side of the substrate with an insulation layer being interposed therebetween, the layers of wiring lines on both sides being interconnected by conducting members provided on the inside walls of through holes going through the core substrate, and the layers of wiring lines on each side of the core substrate being connected with each other by vias of a conductor material going through the interposed insulation layer, the method comprising, on each of sides of the core substrate, alternately forming a layer of wiring lines and an insulation layer while connecting an lower layer of wiring lines with an upper layer of wiring lines by vias, wherein the conducting member on the inside wall of the through hole and the via are formed in separate steps.

2. The method of claim 1, which comprises the following steps:

providing a core substrate having a patterned first layer of wiring lines formed on each side thereof,

forming an insulation layer on each side of the core substrate to cover the entire area of the substrate provided with the first layer of wiring lines,

forming through holes extending from one side to the other side of the core substrate piercing through the insulation layer on both sides of the core substrate and the core substrate itself,

forming via holes in the insulation layer on each side of the core substrate to expose parts of the layer of wiring lines at the bottom,

forming a continuous conductor layer to cover the inside walls of the through holes, the insulation layer, and the exposed parts of the layer of wiring lines,

filling the through holes with an insulation material,

filling the via holes with a conductor material,

forming a conductor layer on the continuous conductor layer covering the insulation layer to provide a lamination of two conductor layers, simultaneously with or separately from the step of filling the via holes, and

patterning the lamination of two conductor layers to thereby provide a second layer of wiring lines.

3. The method of claim 2, wherein the step of forming through holes is carried out prior to the step of forming via holes.

4. The method of claim 2, wherein the step of forming via holes is carried out prior to the step of forming through holes.

5. The method of claim 2, wherein the continuous conductor layer is formed by electroless plating or sputtering and subsequent electroplating.

6. The method of claim 2, wherein the step of filling the via holes is carried out by electroless plating or sputtering and subsequent electroplating.

7. The method of claim 1, which comprises the following steps:

providing a core substrate, forming through holes in the core substrate,

forming a continuous conductor layer on each side of the substrate and the inside walls of the through holes,

filling the through holes with an insulation material,

patterning the continuous conductor layer to form a first layer of wiring lines,

forming an insulation layer on each side of the core substrate to cover the entire area of the substrate provided with the first layer of wiring lines,

forming via holes in the insulation layer on each side of the core substrate to expose parts of the first layer of wiring lines at the bottom,

filling the via holes with a conductor material,

forming a conductor layer on the insulation layer, simultaneously with or separately from the step of filling the via holes, and

patterning the conductor layer to thereby provide a second layer of wiring lines.

8. The method of claim 7, wherein, prior to the step of patterning the continuous conductor layer, an additional conductor layer is formed on the continuous conductor layer to provide a lamination of two conductor layers on the insulation layer, and the lamination of two conductor layers is then patterned to thereby form the first layer of wiring lines.

9. The method of claim 7, wherein the continuous conductor layer is formed by electroless plating or sputtering and subsequent electroplating.

10. The method of claim 7, wherein the step of filling the via holes is carried out by electroless plating or sputtering and subsequent electroplating.

11. The method of claim 1, which comprises the following steps:

providing a core substrate having a first layer of patterned wiring lines formed on each side thereof,

forming an insulation layer on each side of the core substrate to cover the entire area of the substrate provided with the first layer of wiring lines,

forming through holes extending from one side to the other side of the core substrate through the insulation layer on both sides of the core substrate and the core substrate itself,

forming a continuous conductor layer to cover the inside walls of the through holes and the insulation layer,

filling the through holes with an insulation material,

patterning the continuous conductor layer to provide a second layer of wiring lines,

forming an additional insulation layer to cover the formerly formed insulation layer provided thereon with the second layer of wiring lines,

forming via holes through the two insulation layers to expose parts of the first layer of wiring lines at the bottom,

filling the via holes with a conductor material, forming a conductor layer on the top of the two insulation layers, simultaneously with or separately from the step of filling the via holes, and

patterning the conductor layer to thereby provide a second layer of wiring lines.

12. The method of claim 11, wherein, prior to the step of patterning the conductor layer to provide a second layer of wiring lines, an additional conductor layer is formed on the continuous conductor layer and the ends of the insulation material filled in the through holes to provide a lamination of two conductor layers, and the lamination of two conductor layers is then patterned to thereby form the second layer of wiring lines.

13. The method of claim 11, wherein the continuous conductor layer is formed by electroless plating or sputtering and subsequent electroplating.

14. The method of claim 11, wherein the step of filling the via holes is carried out by electroless plating or sputtering and subsequent electroplating.