Method of forming intermediate structures in porous substrates in which electrical and optical microdevices are fabricated and intermediate structures formed by the same

• US 6,350,623 B1
• Filed: 10/27/2000
• Issued: 02/26/2002
• Est. Priority Date: 10/29/1999
• Status: Expired due to Fees

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Fuenzalida, V., Scherer, Axel, Doll, Theodore
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Roman, Angel
• Application Number:
  US09/699,221
• Time in Patent Office: 487 Days
• Field of Search: 438/21, 438/381, 438/408, 438/455, 438/459, 438/409, 438/960, 438/3, 438/108, 438/612, 438/667
• US Class Current: 438/3
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: G02B 6/1225 comprising photonic band-gap structures or photonic lattices
• CPC Class Codes: H01F 41/043 by thick film techniques
• CPC Class Codes: H01G 9/055 Etched foil electrodes
• CPC Class Codes: H01L 21/0334 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/96 Porous semiconductor

Abstract

The invention is a method of fabricating electrically passive components or optical elements on top or underneath of an integrated circuit by using a porous substrate that is locally filled with electrically conducting, light emitting, insulating or optically diffracting materials. The invention is directed to a method of fabricating electrically passive components like inductors, capacitors, interconnects and resistors or optical elements like light emitters, waveguides, optical switches of filters on top or underneath of an integrated circuit by using porous material layer that is locally filled with electrically conducting, light emitting, insulating or optically diffracting materials. In the illustrated embodiment the fabrication of voluminous, solenoid-type inductive elements in a porous insulating material by standard back- and front-side-lithography and contacting these two layers by electroplating micro-vias through the pores is described. By using a very dense interconnect spacing, an inter-pore capacitor structure is obtained between the metalized pores and the pore walls utilized as insulators.

Claims

1. A method of fabricating an intermediate structure in a porous substrate in which microdevices are fabricated and which porous substrate has a frontside with a plurality of open pores and an opposing backside wherein said plurality of pores are closed, said method comprising:

disposing a patterned photolithographed mask on said backside; and

removing selected portions of said backside to leave a portion of said porous substrate intact to define open pore portions and to leave a portion of said porous substrate with said backside removed to define a plurality of disconnected segments which in turn define pore walls for a subplurality of doubly-opened pores which are open on each opposing end of said pore,

thereby forming an intermediate structure in which microdevices may be formed.

2. The method of claim 1 further comprising selectively removing said plurality of disconnected segments to form a plurality of disconnected open pore substrate portions as an intermediate structure in which microdevices may be formed.

3. The method of claim 1 further comprising electroplating said backside to fill said doubly-opened pores with a filler material to define a filled pore portion and to create a starting electroplated layer on said backside.

4. The method of claim 3 further comprising further electroplating said backside to form a final electroplated layer of material thereon acting as a backing layer.

5. The method of claim 3 further comprising disposing an insulating layer on said backside prior to further electroplating said backside to form a final electroplated layer in order to reduce thickness of said final electroplated layer on said backside.

6. The method of claim 4 further comprising selectively removing open pore substrate portions to leave a filled pore portion.

7. The method of claim 6 further comprising removing said final electroplated layer on said backside to leave a free standing filled pore portion.

8. The method of claim 7 further comprising utilizing said free standing filled pore portion as an interconnect layer in a flip-chip hybrid circuit.

9. The method of claim 7 further comprising utilizing said free standing filled pore portion as a two-dimensional Zebra-connector between two surfaces bearing contact bumps which in turn are attached to connectors formed on both sides of said Zebra-connector.

10. The method of claim 1 further comprising:

filling in said disconnected segments with a filler material;

selectively filling in said open pore portions with a conductive material and forming an array of two parallel rows of connectors through said porous substrate; and

disposing metallizations on said frontside and backside of said porous substrate coupling alternate ones of said connectors in each of said two parallel rows of connectors to form a conductive coil in said porous substrate.

11. The method of claim 10 where filling in said disconnected segments with a filler material comprises filling in said disconnected segments with a magnetically permeable material.

12. The method of claim 10 where disposing metallizations on said frontside and backside of said porous substrate comprises disposing diagonal metallizations on said frontside and backside of said porous substrate to connect opposing connectors in said two rows.

13. The method of claim 10 where disposing metallizations on said frontside and backside of said porous substrate comprises disposing double metallizations which are insulated from each other so that two electrically separate coils are formed in said porous substrate.

14. The method of claim 13 where forming an array of two parallel rows of connectors through said porous substrate further comprises forming four parallel rows of connectors so that two concentric coils are formed therefrom.

15. The method of claim 10 further comprising forming a conductive contact on said frontside and backside of said porous substrate and coupling each of said conductive contacts with one end of said coil.

16. The method of claim 1 further comprising:

selectively removing said open pore substrate portions to leave said plurality of disconnected segments;

disposing a first conductive layer on a first end of said disconnected segments;

disposing a second conductive layer on said pore walls, on said first conductive layer exposed in said pore, and on a second end of said disconnected segments opposing said first end;

disposing an insulating layer on said second conductive layer;

disposing a third conductive layer on said insulating layer to fill said pores and to form a conductive backside layer so that a capacitor is formed.

17. The method of claim 16 further comprising electroplating a starting layer on said first end of said disconnected segments.

18. The method of claim 16 where disposing a first conductive layer on a first end of said disconnected segments comprises electroplating a conductive partial layer partially extending into said pores, disposing a seed layer within said pores and on said second end of said disconnected segments and on said conductive partial layer within said pores, and electroplating a conductive final layer on said seed layer, said conductive partial layer, seed layer and conductive final layer comprising said second conductive layer.

19. The method of claim 16 where disposing an insulating layer on said second conductive layer comprises partially converting said conductive final layer into a first insulating layer and disposing a second insulating layer thereon.

20. The method of claim 16 where disposing a third conductive layer on said insulating layer comprises disposing a second seed layer on said insulating layer and electroplating an electrode layer thereon to fill said pores and to provide said backing.