Memory cell having a vertical transistor with buried source/drain and dual gates

• US 6,350,635 B1
• Filed: 08/24/1998
• Issued: 02/26/2002
• Est. Priority Date: 07/08/1997
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard, Noble, Wendell P.
• Primary Examiner(s): CRANE, SARA W
• Application Number:
  US09/139,164
• Time in Patent Office: 1,282 Days
• Field of Search: 257/296, 257/302, 257/304, 257/306, 257/330, 257/331, 257/332, 257/334, 257/347, 438/268, 438/270, 438/156, 438/157, 438/164
• US Class Current: 438/156
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/488 Word lines

Abstract

An integrated circuit and fabrication method includes a memory cell for a dynamic random access memory (DRAM). Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried first and second gates are provided for each access transistor on opposing sides of the pillars. Buried word lines extend in trenches orthogonal to the bit lines. The buried word lines interconnect ones of the first and second gates. In one embodiment, unitary gates are interposed and shared between adjacent pillars for gating the transistors therein. In another embodiment, separate split gates are interposed between and provided to the adjacent pillars for separately gating the transistors therein. In one embodiment, the memory cell has a surface area that is approximately 4 F², where F is a minimum feature size. Bulk-semiconductor and semiconductor-on-insulator (SOI) embodiments are provided.

Claims

1. A method of forming an integrated circuit, the method comprising:

forming a first layer on a substrate, the first layer having a first conductivity type;

forming a second layer on the first layer, the second layer having a second conductivity type;

forming a third layer on the second layer, the third layer having the first conductivity type;

forming a first plurality of substantially parallel trenches extending through the third layer, the second layer, the first layer, and extending at least partially into the substrate, the first plurality of trenches defining a plurality of semiconductor bars;

removing an amount of the substrate sufficient to at least partially undercut the plurality of semiconductor bars;

forming a first insulating layer between the substrate and the plurality of semiconductor bars, the insulating layer underlying the plurality of semiconductor bars;

forming a second plurality of substantially parallel row trenches substantially orthogonally to the first plurality of trenches, the second plurality of substantially parallel row trenches extending through the third layer, the second layer, and extending partially through the first layer such that the first layer serves as a plurality of bit lines;

forming a second insulating layer substantially covering a surface of the second plurality of trenches;

forming conductors in the second plurality of trenches, each conductor comprising a conductive layer and being disposed in one of the second plurality of trenches; and

coupling the bit lines and the conductors to addressing circuitry.

2. The method of claim 1, further comprising forming a third insulating layer on the third layer to form a plurality of storage capacitors.

3. The method of claim 1, wherein forming the first insulating layer between the substrate and the column bars comprises oxidizing a portion of the substrate to form the first insulating layer.

4. The method of claim 3, further comprising filling the second plurality of trenches with insulating material by oxidizing a portion of the substrate exposed in the second plurality of trenches.

5. The method of claim 1, further comprising splitting each word line into two word lines, the two word lines being electrically isolated from each other.

6. The method of claim 1, wherein the plurality of column trenches extend into the substrate at least 0.6 μ

m below the surface of the substrate.

7. A method of forming an integrated circuit, the method comprising:

forming a first layer of a first conductivity type on a substrate, the first layer having a thickness in the range of 0.2 μ

m to 0.5 μ

m, the first layer comprising a more heavily doped layer within it, the more heavily doped layer having a thickness in the range of 0.1 μ

m to 0.25 μ

m;

forming a second layer of a second conductivity type on the first layer;

forming a third layer of the first conductivity type on the second layer, the third layer having a thickness in the range of 0.2 μ

m to 0.5 μ

m;

forming a plurality of substantially parallel column trenches extending through the third, the second, and the first layers sufficiently deep to reach the substrate, the plurality of column trenches defining a plurality of column bars, wherein the width of a trench on the surface of the substrate is no more than 1 μ

m;

forming a plurality of substantially parallel row trenches defining a plurality of row bars, the row trenches being substantially orthogonal to the column trenches, the plurality of row trenches extending through the third, the second and partially through the first layers, terminating above the more heavily doped layer, such that the more heavily doped layer serves as a plurality of bit lines;

forming word lines in the plurality of row trenches, each word line comprising a conductive layer and being disposed in a row trench; and

coupling the bit lines and the word lines to addressing circuitry.

8. The method of claim 7, further comprising forming a first insulating layer of about 10 nm thick on the third layer and a second insulating layer of about 100 nm thick on the first insulating layer before forming the plurality of the column trenches, the first and second insulating layers being removed after forming the word lines in the plurality of row trenches.

9. The method of claim 7, further comprising filling the plurality of column trenches with an insulating material after forming the plurality of column trenches.

10. The method of claim 7, further comprising forming an insulating layer on a surface of the row trenches before forming the word lines.

11. The method of claim 7, further comprising splitting each word line into two word lines, the two word lines being electrically isolated from each other.

12. A method of fabricating an integrated circuit, the method comprising:

providing a substrate;

forming a plurality of bit lines on the substrate;

forming a plurality of access transistors on each of the bit lines, each access transistor including a first source/drain region shared by at least a portion of the bit line, a body region and a second source/drain region formed vertically thereupon;

forming a plurality of isolation trenches in the substrate and orthogonal to the bit lines, each trench located between access transistors on the orthogonal bit lines;

forming in a first one of the trenches a first word line that controls conduction between first and second source/drain regions of access transistors that are adjacent to a first side of the first trench;

forming in a second one of the trenches, adjacent to the first trench, a second word line that controls conduction between first and second source/drain regions of access transistors that are adjacent to a first side of the second trench; and

coupling the bit lines, the first word line and the second word line to addressing circuitry.

13. The method of claim 12, wherein the first word line also controls conduction between first and second source/drain regions of access transistors that are adjacent to a second side of the first trench.

14. The method of claim 12, wherein the second word line also controls conduction between first and second source/drain regions of access transistors that are adjacent to a second side of the second trench.

15. The method of claim 12, further comprising forming, in the first trench, another first word line, which controls conduction between first and second source/drain regions of access transistors that are adjacent to a second side of the first trench.

16. The method of claim 12, further comprising forming, in the second trench, another second word line, which controls conduction between first and second source/drain regions of access transistors that are adjacent to a second side of the second trench.

17. A method of fabricating an integrated circuit, the method comprising:

forming a first conductivity type first source/drain region layer on a substrate;

forming a second conductivity type body region layer on the first source/drain layer;

forming a first conductivity type second source/drain region layer on the body region layer;

forming a plurality of substantially parallel column isolation trenches extending through the second source/drain region layer, the body region layer, and the first source/drain region layer, thereby forming column bars between the column isolation trenches;

providing an isolation material in the column isolation trenches;

forming a plurality of substantially parallel row isolation trenches, orthogonal to the column isolation trenches, extending through the second source/drain region layer, the body region layer, and at least partially into the first source/drain region layer in the column bars, such that the first source/drain region layer in the column bars serves as a bit line, the row isolation trenches also extending at least partially into the isolation material in the column isolation trenches, thereby forming row bars between the row isolation trenches;

forming an insulating layer at the base of the row isolation trenches;

forming conductive word lines in the row isolation trenches; and

coupling the bit lines and the word lines to addressing circuitry.

18. The method of claim 17, further comprising forming an insulating layer underlying the column bars.

19. The method of claim 17, further comprising etching portions of the word lines to provide separate word lines on each side of the row isolation trenches.