Simplified graded LDD transistor using controlled polysilicon gate profile

• US 6,350,639 B1
• Filed: 04/10/2001
• Issued: 02/26/2002
• Est. Priority Date: 09/28/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Cheung, Patrick K., Steffan, Paul J., Yu, Allen S.
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): CHEN, JACK S J
• Application Number:
  US09/832,684
• Time in Patent Office: 322 Days
• Field of Search: 438/199, 438/200, 438/210, 438/223, 438/224, 438/227, 438/228, 438/229, 438/230, 438/231, 438/232
• US Class Current: 438/199
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66598 forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer

Abstract

An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a first polysilicon gate, wherein the first polysilicon gate has sidewalls with sloped profiles and the sloped profiles are used as masks during the ion implantation of the LDD structures to space the resultant LDD structures away from the edges of second polysilicon gates to be formed subsequently with substantially vertical profiles.

Claims

1. A method for manufacturing a complementary MOS structure on a semiconductor substrate, comprising:

forming a gate oxide layer over the semiconductor substrate;

forming a polysilicon layer over said gate oxide layer;

forming a first mask layer over said polysilicon layer;

patterning and etching said first mask layer to form a first gate mask and a second gate mask;

anisotropically etching said polysilicon layer to form a first polysilicon gate and a second polysilicon gate, each of said first polysilicon gate and said second polysilicon gate has sidewalls with sloped profiles, said sidewalls of said first polysilicon gate and said sidewalls of said second polysilicon gate respectively shield a first portion and a second portion of the semiconductor substrate;

forming a second mask layer over a portion of the semiconductor substrate containing said second polysilicon gate;

implanting the semiconductor substrate in a first implantation with a first dopant of a first conductivity type at a first energy and a first concentration to form one or more first shallow extension junctions in the semiconductor substrate;

removing said second mask layer;

forming a third mask layer over a portion of the semiconductor substrate containing said first polysilicon gate and said one or more first shallow extension junctions;

implanting the semiconductor substrate in a second implantation with a second dopant of a second conductivity type at a second energy and a second concentration to form one or more second shallow extension junctions and a doped resistor region in said semiconductor substrate;

anisotropically etching said first polysilicon gate and said second polysilicon gate to respectively form a third polysilicon gate and a fourth polysilicon gate using said first gate mask and said second gate mask as masks, wherein each of said third polysilicon gate and said fourth polysilicon gate has sidewalls with substantially vertical profiles;

removing said first gate mask and said second gate mask;

forming a resistor protect layer over said gate oxide layer, said doped resistor region, said third polysilicon gate, and said fourth polysilicon gate;

selectively masking said resistor protect layer with a resistor protect mask on said doped resistor region where a resistor isolation is to be formed;

anisotropically etching said resistor protect layer to form said resistor isolation under said resistor protect mask, a first sidewall spacer around said third polysilicon gate, said first sidewall spacer shields portions of said first shallow extension junctions, and a second sidewall spacer around said fourth polysilicon gate, said second sidewall spacer shields portions of said second shallow extension junctions, wherein said anisotropically etching of said resistor protect layer has over-etching said resistor protect layer to reduce dimensions of said first sidewall spacer and said second sidewall spacer so that top portions of said third polysilicon gate and said fourth polysilicon gate are exposed; and

removing said resistor protect mask to expose said resistor isolation.

2. The method as claimed in claim 1 wherein:

implanting the semiconductor substrate in said first implantation includes penetrating portions of said sidewalls of said first polysilicon gate with said first dopant to form said first shallow extension junctions, said first shallow extension junctions are graded junctions; and

implanting the semiconductor in said second implantation includes penetrating portions of said sidewalls of said second polysilicon gate to form said second shallow extension junctions, said second shallow extension junctions are graded junctions.

3. The method as claimed in claim 1 wherein:

implanting the semiconductor substrate in said first implantation with said first dopant forms first deep junctions in a portion of the semiconductor substrate not shielded by said first polysilicon gate and adjacent said first shallow extension junctions; and

implanting the semiconductor substrate in said second implantation with said second dopant forms second deep junctions in a portion of the semiconductor substrate not shielded by said second polysilicon gate and adjacent said second shallow extension junctions.

4. The method as claimed in claim 1 including:

forming a metallic layer over said doped resistor region, said third polysilicon gate, said fourth polysilicon gate, said first sidewall spacer, said second sidewall spacer, said first shallow extension junctions, and said second shallow extension junctions after removing said resistor protect mask to expose said resistor isolation; and

annealing the semiconductor substrate to form a metallic salicide over the top portions of said third polysilicon gate and said fourth polysilicon gate, and portions of said first and second shallow extension junctions that are not shielded by said first and said second sidewall spacers.

5. A method for manufacturing a complementary MOS structure on a semiconductor substrate, comprising:

forming a gate oxide layer over the semiconductor substrate;

forming a polysilicon layer over said gate oxide layer;

forming a first mask layer over said polysilicon layer;

patterning and etching said first mask layer to form a first gate mask and a second gate mask;

anisotropically etching said polysilicon layer to form a first polysilicon gate and a second polysilicon gate, each of said first polysilicon gate and said second polysilicon gate has sidewalls with sloped profiles, said sidewalls of said first polysilicon gate and said sidewalls of said second polysilicon gate respectively shield a first portion and a second portion of the semiconductor substrate;

forming a second mask layer over a portion of the semiconductor substrate containing said second polysilicon gate;

implanting the semiconductor substrate in a first implantation with a first dopant of a first conductivity type at a first energy and a first concentration to form one or more first shallow extension junctions in the semiconductor substrate and first deep junctions in a portion of the semiconductor substrate not shielded by said first polysilicon gate and adjacent said first shallow extension junctions, and wherein said first dopant penetrates portions of said sidewalls of said first polysilicon gate to form said first shallow extension junctions, said first shallow extension junctions are graded junctions;

removing said second mask layer;

forming a third mask layer over a portion of the semiconductor substrate containing said first polysilicon gate and said one or more first shallow extension junctions;

implanting the semiconductor substrate in a second implantation with a second dopant of a second conductivity type at a second energy and a second concentration to form one or more second shallow junctions and a doped resistor region in said semiconductor substrate, and second deep junctions in a portion of the semiconductor substrate not shielded by said second polysilicon gate and adjacent said second shallow extension junctions, wherein said second dopant penetrates portions of said sidewalls of said second polysilicon gate to form said second shallow extension junctions, said second shallow extension junctions are graded junctions;

anisotropically etching said first polysilicon gate and said second polysilicon gate to respectively form a third polysilicon gate and a fourth polysilicon gate using said first gate mask and said second gate mask as masks, wherein said each of said third polysilicon gate and said fourth polysilicon gate has sidewalls with substantially vertical profiles;

removing said first gate mask and said second gate mask;

forming a resistor protect layer over said gate oxide layer, said doped resistor region, said third polysilicon gate, and said fourth polysilicon gate;

selectively masking said resistor protect layer with a resistor protect mask on said doped resistor region where a resistor isolation is to be formed;

anisotropically etching said resistor protect layer to form said resistor isolation under said resistor protect mask, a first sidewall spacer around said third polysilicon gate, said first sidewall spacer shields portions of said first deep junctions, and a second sidewall spacer around said fourth polysilicon gate, said second sidewall spacer shields portions of said second deep junctions, wherein anisotropically etching said resistor protect layer has over-etching said resistor protect layer to reduce dimensions of said first sidewall spacer and said second sidewall spacer so that top portions of said third polysilicon gate and said fourth polysilicon gate are exposed; and

removing said resistor protect mask to expose said resistor isolation.

6. The method as claimed in claim 5 including:

forming a metallic layer over said doped resistor region, said third polysilicon gate, said fourth polysilicon gate, said first sidewall spacer, said second sidewall spacer, said first deep junctions, and said second deep junctions after removing said resistor protect mask to expose said resistor isolation; and

annealing the semiconductor substrate to form a metallic salicide over the top portions of said third polysilicon gate and said fourth polysilicon gate, and portions of said first and second deep junctions that are not shielded by said first and said second sidewall spacers.