Process for manufacturing nonvolatile memory cells with dimensional control of the floating gate regions

• US 6,350,652 B1
• Filed: 06/01/2000
• Issued: 02/26/2002
• Est. Priority Date: 10/23/1998
• Status: Expired due to Term

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Patelmo, Matteo, Vajana, Bruno, Libera, Giovanna Dalla
• Primary Examiner(s): DANG, TRUNG Q
• Application Number:
  US09/587,214
• Time in Patent Office: 635 Days
• Field of Search: 438/257, 438/258, 438/264, 438/266
• US Class Current: 438/257
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor

Abstract

A manufacturing process including: forming a first insulating region on top of an active area; forming a tunnel region at the side of the first insulating region; depositing and defining a semiconductor material layer using a floating gate mask to form a floating gate region. The floating gate mask has an opening with an internal delimiting side extending at a preset distant from a corresponding outer delimiting side of the mask, so that the floating gate region forms inner a hole, and the tunnel region is defined, as regards its length, by the floating gate ask alone. The hole is filled with a dielectric material layer. The surface of the floating gate region is planarized, and an insulating region of dielectric material is made. A control gate region and conductive regions in the active area are then formed.

Claims

1. A process for manufacturing electronic devices having floating gate nonvolatile memory cells, comprising:

defining an active area in a substrate of semiconductor material;

forming a first insulating region on top of said active area;

depositing a first dielectric material layer on top of said substrate;

said first dielectric material layer comprising a tunnel area;

forming a floating gate region on top of said first dielectric material layer and on top of said first insulating region, said forming the floating gate region comprising depositing a first semiconductor material layer on top of said dielectric material layer and of said first insulating region and selectively removing said first semiconductor material layer using a floating gate mask having an outer delimiting side, an opening with an internal delimiting side facing said outer delimiting side at a preset distance, in that said step of selectively removing comprises the step of removing said first semiconductor material layer at the side of said external delimiting side and below said opening, forming a hole in said floating gate region, and filling said hole with an electrically insulating material;

forming a second insulating region surrounding said floating gate region;

forming a control gate region on top of said floating gate region; and

forming conductive regions in said active area.

2. The process of claim 1 wherein filling said hole comprises depositing a second dielectric material layer, said second dielectric material layer comprising a filling region that extends in said hole of said floating gate region.

3. The process of claim 1 wherein said floating gate mask has an external perimetral edge of rectangular shape, in that said opening has an internal perimetral edge of rectangular shape, in that said external delimiting side and said internal delimiting side are parallel to one another, facing one another, and delimit between each other a mask portion defining a length dimension of said tunnel area.

4. The process of claim 1 wherein said opening is arranged astride of or laterally to said first insulating region.

5. The process of claim 2, further comprising, after depositing said second dielectric material layer, planarizing and removing said second dielectric material layer from the upper surface of said floating gate region.

6. The process of claim 5 wherein planarizing and removing is carried out using the CMP technique.

7. The process of claim 5, further comprising, before planarizing and removing, selectively removing said second dielectric material layer on top of said substrate, at a distance from said floating gate region, and forming lateral insulation regions on the sides of said floating gate region.

8. The process of claim 7 wherein said floating gate mask has externally first dimensions, wherein selectively removing said second dielectric material layer is carried out using a second mask having second dimensions larger than said first dimensions, and wherein forming a second insulating region comprises depositing an insulating material layer and selectively removing said insulating material layer using a third mask having third dimensions larger than said first dimensions and smaller than said second dimensions.

9. The process of claim 1 wherein said cell is an EEPROM cell, and further comprising forming a selection transistor laterally to and at a distance from said tunnel region.

10. A manufacturing process, comprising:

forming a first insulating region on top of an active area in a substrate of semiconductor material;

forming a tunnel region at the side of the first insulating region;

depositing a layer of semiconductor material; and

defining the layer of semiconductor material using a floating gate mask to form a floating gate region, the floating gate mask having an opening with an internal delimiting side extending at a preset distance from a corresponding outer delimiting side of the mask to form a hole in the floating gate region by the floating gate mask.

11. The process of claim 10, wherein the tunnel region is defined with respect to its length by the floating gate mask alone.

12. The method of claim 10, further comprising filling the hole in the floating gate region with dielectric material and forming an insulating region of dielectric material over the floating gate region.

13. The method of claim 12 wherein filling the hole with dielectric material further comprises planarizing the surface of the floating gate region prior to forming the insulating region of dielectric material.

14. The method of claim 13 wherein filling the hole with dielectric material and planarizing the floating gate region includes forming side insulation regions on the sides of the floating gate region.

15. A process for manufacturing nonvolatile memory cells with dimensional control of floating gate regions, the method comprising:

forming a floating gate mask having an opening over a first polycrystalline silicon layer on a substrate of semiconductor material;

etching the first polycrystalline silicon layer to form a floating gate region having a hole formed under the opening in the floating gate mask;

depositing a layer of dielectric material to fill the hole in the floating gate region and to define a tunnel area under the floating gate region;

depositing a layer of dielectric material to fill the hole in the floating gate region; and

planarizing the surface above the floating gate region to remove the dielectric material from the surface above the floating gate region and to leave the dielectric material at the sides of the floating gate region and in the hole of the floating gate region.

16. The method of claim 15, further comprising:

forming an interpoly dielectric layer to seal the floating gate region on the top and at least a portion of the sides thereof;

growing a high-voltage oxide; and

depositing and shaping a second polycrystalline silicon layer to form a control gate region.