Spacer etch method for semiconductor device

• US 6,350,696 B1
• Filed: 09/28/2000
• Issued: 02/26/2002
• Est. Priority Date: 09/28/2000
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Shields, Jeffrey A., Erhardt, Jeffrey P.
• Primary Examiner(s): GOUDREAU, GEORGE A
• Application Number:
  US09/671,209
• Time in Patent Office: 516 Days
• Field of Search: 438/305, 438/592, 438/595, 438/655, 438/682, 438/704, 438/723, 438/734, 438/743, 438/750, 438/756, 438/696
• US Class Current: 438/704
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET

Abstract

Spacers are formed on a semiconductor device by depositing a spacer layer on the semiconductor device. The semiconductor device is subjected to an anisotropic etching process to leave at least a portion of the spacer layer covering the semiconductor device. The semiconductor device is then subjected to an isotropic etching process to form the spacers on the semiconductor device.

Claims

1. A method of forming spacers on a semiconductor device, comprising:

providing a semiconductor substrate;

forming a plurality of gate electrodes on the semiconductor substrate using polysilicon;

forming an insulating layer between each of the gate electrodes and the semiconductor substrate, each of the insulating layers comprising an oxide-nitride-oxide material to insulate the gate electrode from the semiconductor substrate;

depositing a spacer layer, comprised of oxide or nitride insulating material, over the gate electrodes and the semiconductor substrate to a thickness of approximately 500 Å

;

anisotropically etching, using a plasma reactive-ion etching process, the spacer layer to leave approximately 400 Å

of the spacer layer covering the semiconductor device; and

isotropically etching, using a dilute hydrofluoric or buffered oxide etching process, the portion of the spacer layer to form the spacers on the semiconductor device, the isotropic etching stopping at the nitride material of the insulating layer.

2. A method of forming spacers on a semiconductor device comprising:

providing a semiconductor substrate;

forming a plurality of gate electrodes on the semiconductor substrate using polysilicon;

forming an insulating layer between each of the gate electrodes and the semiconductor substrate, each of the insulating layers comprising an oxide-nitride-oxide material to insulate the gate electrode from the semiconductor substrate;

depositing a spacer layer, comprised of oxide or nitride insulating material, over the gate electrodes and the semiconductor substrate to a thickness of approximately 2,500 Å

;

anisotropically etching, using a plasma reactive-ion etching process, the spacer layer to leave approximately 400 Å

of the spacer layer covering the semiconductor device; and

isotropically etching, using a dilute hydrofluoric or buffered oxide etching process, the portion of the spacer layer to form the spacers on the semiconductor device, the isotropic etching stopping at the nitride material of the insulating layer.

3. A method of forming spacers on a semiconductor device, comprising:

providing a semiconductor substrate;

forming a plurality of gate electrodes on the semiconductor substrate using polysilicon;

forming an insulating layer between each of the gate electrodes and the semiconductor substrate, each of the insulating layers comprising an oxide-nitride-oxide material to insulate the gate electrode from the semiconductor substrate;

depositing a spacer layer, comprised of oxide or nitride insulating material, over the gate electrodes and the semiconductor substrate to a thickness of 1,000 Å

;

anisotropically etching, using a plasma reactive-ion etching process, the spacer layer to leave 400 Å

of the spacer layer covering the semiconductor device; and

isotropically etching, using a dilute hydrofluoric or buffered oxide etching process, the portion of the spacer layer to form the spacers on the semiconductor device, the isotropic etching stopping at the nitride material of the insulating layer.