MOS-gated device having a buried gate and process for forming same
First Claim
1. An improved trench MOS-gated device comprising:
- a substrate comprising doped monocrystalline silicon semiconductor material;
a doped upper layer disposed on said substrate, said upper layer having an upper surface and comprising at said upper surface a plurality of heavily doped body regions having a first polarity, said body regions overlying a drain region in said upper layer, said upper layer further comprising at said upper surface a plurality of heavily doped source regions having a second polarity and extending from said upper surface to a selected depth in said upper layer; and
a gate trench separating one of said source regions from a second source region, said trench extending from said upper surface of said upper layer to said drain region, said trench having a floor and sidewalls comprising a layer of dielectric material, said trench being partially filled with a conductive gate material to a selected level substantially below the upper surface of the upper layer and the remainder of said partially filled trench being filled with an isolation layer of dielectric material overlying and directly located on said gate material, said overlying layer of dielectric material in said trench having an upper surface that is substantially coplanar with said upper surface of said upper layer.
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Abstract
An improved trench MOS-gated device comprises a monocrystalline semiconductor substrate on which is disposed a doped upper layer. The upper layer includes at an upper surface a plurality of heavily doped body regions having a first polarity and overlying a drain region. The upper layer further includes at its upper surface a plurality of heavily doped source regions having a second polarity opposite that of the body regions A gate trench extends from the upper surface of the upper layer to the drain region and separates one source region from another. The trench has a floor and sidewalls comprising a layer of dielectric material and contains a conductive gate material filled to a selected level and an isolation layer of dielectric material that overlies the gate material and substantially fills the trench. The upper surface of the overlying layer of dielectric material in the trench is thus substantially coplanar with the upper surface of the upper layer. A process for forming an improved MOS-gate device provides a device whose gate trench is filled to a selected level with a conductive gate material, over which is formed an isolation dielectric layer whose upper surface is substantially coplanar with the upper surface of the upper layer of the device.
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Citations
18 Claims
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1. An improved trench MOS-gated device comprising:
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a substrate comprising doped monocrystalline silicon semiconductor material;
a doped upper layer disposed on said substrate, said upper layer having an upper surface and comprising at said upper surface a plurality of heavily doped body regions having a first polarity, said body regions overlying a drain region in said upper layer, said upper layer further comprising at said upper surface a plurality of heavily doped source regions having a second polarity and extending from said upper surface to a selected depth in said upper layer; and
a gate trench separating one of said source regions from a second source region, said trench extending from said upper surface of said upper layer to said drain region, said trench having a floor and sidewalls comprising a layer of dielectric material, said trench being partially filled with a conductive gate material to a selected level substantially below the upper surface of the upper layer and the remainder of said partially filled trench being filled with an isolation layer of dielectric material overlying and directly located on said gate material, said overlying layer of dielectric material in said trench having an upper surface that is substantially coplanar with said upper surface of said upper layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification