Low-K sub spacer pocket formation for gate capacitance reduction

• US 6,351,013 B1
• Filed: 07/13/1999
• Issued: 02/26/2002
• Est. Priority Date: 07/13/1999
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Tran, Khanh, Luning, Scott, Wu, David
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Rao, Shrinivas H.
• Application Number:
  US09/352,339
• Time in Patent Office: 959 Days
• Field of Search: 257/372, 257/368, 257/369, 257/717, 257/900, 257/69, 257/204, 257/305, 438/184, 438/230, 438/265, 438/303, 438/595
• US Class Current: 257/368
• CPC Class Codes: H01L 21/02134 the material comprising hydrogen silsesquioxane, e.g. HSQ
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/3124 layers comprising hydrogen silsesquioxane
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66598 forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

The capacitance between the gate electrode and the source/drain regions of a semiconductor device is reduced by forming sub-spacers of a low dielectric constant (K) material at the corners of the gate electrode above the source/drain regions. Subsequently, insulating sidewall spacers are formed over the sub-spacers to shield-shallow source/drain regions from subsequent impurity implantations. The resulting semiconductor device exhibits reduced capacitance between the gate electrode and the source/drain regions, while maintaining circuit reliability.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a dielectric layer formed on the semiconductor substrate;

a gate electrode having an upper surface and side surfaces formed on the dielectric layer;

first sidewall spacers, comprising a first material having a low dielectric constant, formed on the side surfaces of the gate electrode;

a shallow source/drain region extending to a first depth below the surface of the semiconductor substrate; and

a moderately or heavily doped source/drain region extending to a second depth greater than the first depths,

wherein the first material has a dielectric constant of about 1.5 to about 3.5.

2. The semiconductor device of claim 1, comprising:

second sidewall spacers, comprising an insulating material, formed adjacent the side surfaces of the gate electrode and over the first sidewall spacers.

3. The semiconductor device of claim 2, wherein the first material comprises hydrogen silesquioxane.

4. The semiconductor device of claim 2, wherein the first material comprises a spin-on glass.

5. The semiconductor device of claim 2, wherein the first material comprises an organo-oxide.

6. The semiconductor device of claim 1, wherein the dielectric layer comprises a silicon oxide and the gate electrode comprises doped polysilicon.