Low-K sub spacer pocket formation for gate capacitance reduction
First Claim
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1. A semiconductor device comprising:
- a semiconductor substrate;
a dielectric layer formed on the semiconductor substrate;
a gate electrode having an upper surface and side surfaces formed on the dielectric layer;
first sidewall spacers, comprising a first material having a low dielectric constant, formed on the side surfaces of the gate electrode;
a shallow source/drain region extending to a first depth below the surface of the semiconductor substrate; and
a moderately or heavily doped source/drain region extending to a second depth greater than the first depths, wherein the first material has a dielectric constant of about 1.5 to about 3.5.
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Abstract
The capacitance between the gate electrode and the source/drain regions of a semiconductor device is reduced by forming sub-spacers of a low dielectric constant (K) material at the corners of the gate electrode above the source/drain regions. Subsequently, insulating sidewall spacers are formed over the sub-spacers to shield-shallow source/drain regions from subsequent impurity implantations. The resulting semiconductor device exhibits reduced capacitance between the gate electrode and the source/drain regions, while maintaining circuit reliability.
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Citations
6 Claims
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1. A semiconductor device comprising:
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a semiconductor substrate;
a dielectric layer formed on the semiconductor substrate;
a gate electrode having an upper surface and side surfaces formed on the dielectric layer;
first sidewall spacers, comprising a first material having a low dielectric constant, formed on the side surfaces of the gate electrode;
a shallow source/drain region extending to a first depth below the surface of the semiconductor substrate; and
a moderately or heavily doped source/drain region extending to a second depth greater than the first depths, wherein the first material has a dielectric constant of about 1.5 to about 3.5. - View Dependent Claims (2, 3, 4, 5, 6)
second sidewall spacers, comprising an insulating material, formed adjacent the side surfaces of the gate electrode and over the first sidewall spacers.
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3. The semiconductor device of claim 2, wherein the first material comprises hydrogen silesquioxane.
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4. The semiconductor device of claim 2, wherein the first material comprises a spin-on glass.
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5. The semiconductor device of claim 2, wherein the first material comprises an organo-oxide.
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6. The semiconductor device of claim 1, wherein the dielectric layer comprises a silicon oxide and the gate electrode comprises doped polysilicon.
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