Semiconductor device and method for manufacturing substrate of the same

• US 6,351,031 B1
• Filed: 03/22/2000
• Issued: 02/26/2002
• Est. Priority Date: 10/12/1999
• Status: Expired due to Term

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Iijima, Makoto, Ueno, Seiji, Morioka, Muneharu, Nukiwa, Masaru
• Primary Examiner(s): Clark, Sheila V.
• Application Number:
  US09/533,173
• Time in Patent Office: 706 Days
• Field of Search: 257/698, 257/783, 257/635, 257/642, 257/643, 257/778, 361/792, 361/795, 361/748, 174/255, 174/258, 174/259, 174/262, 174/263, 174/264, 174/266
• US Class Current: 257/698
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3157 Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/15151 the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H05K 1/0393 : Flexible materials H05K1/038 takes precedence; specific organic compositions are classified in H05K1/0313 and subgroups
• CPC Class Codes: H05K 2201/0195 : Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
• CPC Class Codes: H05K 2201/0355 : Metal foils
• CPC Class Codes: H05K 2201/09563 : Metal filled via plated through-hole filled with insulating material H05K2201/0959
• CPC Class Codes: H05K 2201/09827 : Tapered, e.g. tapered hole, via or groove bevelled, chamferred or tapered edge H05K2201/09154
• CPC Class Codes: H05K 2203/016 : Temporary inorganic, non-metallic carrier, e.g. for processing or transferring
• CPC Class Codes: H05K 2203/063 : of preperforated insulating layer
• CPC Class Codes: H05K 2203/0733 : Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
• CPC Class Codes: H05K 3/205 : using a pattern electroplated or electroformed on a metallic carrier
• CPC Class Codes: H05K 3/386 : by the use of an organic polymeric bonding layer, e.g. adhesive
• CPC Class Codes: H05K 3/423 : characterised by electroplating method
• CPC Class Codes: H05K 3/4617 : characterized by laminating only or mainly similar single-sided circuit boards
• CPC Class Codes: H05K 3/4635 : laminating flexible circuit boards using additional insulating adhesive materials between the boards

Abstract

A semiconductor device includes a multi-flexible substrate and semiconductor chips mounted thereon. The multi-flexible substrate is configured such that organic insulation substrate layers and filmy adhesive layers are alternatively stacked together and wiring layers formed therein are interconnected by means of vias. Each of the vias consisting of a via-hole which is formed penetrating both the organic insulation substrate layers and the filmy adhesive layers and a metal via member 26 which is provided in the via-hole and made of an identical material. A method of manufacturing the multi-flexible substrate for the semiconductor device is also disclosed.

Claims

1. A semiconductor device, comprising:

a substrate having a plurality of organic insulation substrate layers and a plurality of adhesive layers which are alternatively stacked, and inter-layer wires which are laid among said stacked layers and are electrically interconnected by using vias; and

a semiconductor chip mounted on said substrate;

said vias each having a via-hole which is formed penetrating said organic insulation substrate layers and said adhesive layers and a metal via member which is disposed in said via-hole and made of an identical material, wherein;

said substrate includes an opening which is formed in a position facing toward said semiconductor chip;

said semiconductor chip is bonded to said substrate by means of a face-down bonding process; and

underfill resin is introduced between said semiconductor chip and said substrate.

2. A semiconductor device, comprising:

a substrate having a plurality organic insulation substrate layers and a plurality of adhesive layers which are alternatively stacked, and inter-layer wires which are laid among said stacked layers and are electrically interconnected by using vias; and

a semiconductor chip mounted on a said substrate;

said vias each having a via-hole which is formed penetrating said organic insulation substrate layers and said adhesive layers and a metal via member which is disposed in said via-hole and made of an identical material, wherein said via-holes are shaped like truncated cones.