Semiconductor wafer test and burn-in

• US 6,351,134 B2
• Filed: 05/07/1999
• Issued: 02/26/2002
• Est. Priority Date: 08/09/1995
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Nihon Micronics
• Original Assignee: International Business Machines Corporation
• Inventors: Leas, James Marc, Gardell, David Lewis, Prilik, Ronald, Koss, Robert William, Van Horn, Jody John, Dingle, Steve Leo, Walker, George Frederick, Perry, Charles Hampton
• Primary Examiner(s): KARLSEN, ERNEST F
• Application Number:
  US09/307,394
• Publication Number:
  US 20020003432A1
• Time in Patent Office: 1,026 Days
• Field of Search: 324/765, 324/754, 324/757, 324/758, 324/762, 324/73.1, 324/72.5
• US Class Current: 324/750.05
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 1/07385 using switching of signals between probe tips and test bed, i.e. the standard contact matrix which in its turn connects to the tester
• CPC Class Codes: G01R 31/2863 Contacting devices, e.g. sockets, burn-in boards or mounting fixtures in general G01R1/04
• CPC Class Codes: G01R 31/2879 related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence

Abstract

An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.

Claims

1. A method for testing or burning-in a plurality of integrated circuit product chips having signal I/O, ground, and power pads, the method comprising the steps of:

a) contacting pads of said plurality of product chips with a test head, wherein said test head comprises a functional test chip;

b) applying power from a power plane in the test head to a first surface of said functional test chip;

c) distributing power from a second surface of said functional test chip to power pads of the product chips; and

d) testing or burning-in the plurality of product chips through said test head.

2. A method as recited in claim 1, wherein said test head further comprises connectors for external connection.

3. The method as recited in claim 1, further comprising the step of providing regulated voltage from a voltage regulator on said test chip or a test from a test circuit on said test chip.

4. The method as recited in claim 3, further comprising the step of varying the regulated voltage.

5. The method as recited in claim 4, wherein said step (b) further comprises the step of providing a reference voltage to one said voltage regulator on an externally accessible reference signal line, wherein said regulator provides said power from said power supply to a power pad of a product chip at a voltage level corresponding to that applied on an said reference signal line.

6. The method as recited in claim 1, further comprising the step of providing electrical connection between the product chips and said functional test chip.

7. The method as recited in claim 3, further comprising gating said voltage regulators to disconnect power from selected product chips.

8. The method as recited in claim 3, further comprising the step of setting a compliance current.

9. The method as recited in claim 8, wherein said compliance current setting is externally controllable.

10. The method as recited in claim 3 further comprising a decoupling capacitor on an output line of said voltage regulator.

11. The method as recited in claim 10, wherein said decoupling capacitor comprises a trench capacitor.

12. The method as recited in claim 1, further comprising the step of disconnecting contact to the signal I/O pads of a product chip.

13. The method as recited in claim 1, wherein said test head comprises a plurality of functional test chips that are separated from other chips on a test wafer on which said functional test chips were formed.

14. The method as recited in claim 1, wherein said product chips are on a product wafer.

15. The method as recited in claim 14, wherein said step (a) comprises contacting substantially all the product chips on the product wafer.

16. The method as recited in claim 1, wherein said test chip is removable from said test head.

17. The method as recited in claim 5, further comprising the step of sensing a voltage difference on a product chip and correspondingly adjusting an output of said voltage regulator so that said voltage difference matches said reference voltage.

18. The method as recited in claim 1, further comprising the step of providing a vacuum, hydraulic, or pneumatic force to provide contact between the product chips and said test head.

19. The method as recited in claim 1, wherein said test head can maintain contact with said pads of said plurality of product chips from about room temperature to about 180 degrees Celsius.

20. The method as recited in claim 1, wherein said test bead is capable of testing and burning-in the plurality of product chips.

21. The method as recited in claim 1, wherein said functional test chip is of opposite electrical conductivity than said plurality of product chips.

22. The method as recited in claim 1, wherein in said distributing step (c) said second surface is a front surface of said functional test chip facing the product chips.

23. The method as recited in claim 1, wherein in said applying step (b) said first surface is a back surface of said functional test chip.

24. A method for testing or burning-in a plurality of integrated circuit product chips having signal I/O, ground, and power pads, the method comprising the steps of:

a) contacting pads of said plurality of product chips with a test head, wherein said test head comprises a functional test chip;

b) applying power from a power supply to a surface of said functional test chip;

c) distributing power from said surface through said functional test chip to power pads of the product chips; and

d) testing or burning-in the plurality of product chips through said test head.