×

Method and apparatus for reducing soft errors in dynamic circuits

  • US 6,351,151 B2
  • Filed: 07/18/2001
  • Issued: 02/26/2002
  • Est. Priority Date: 12/23/1999
  • Status: Expired due to Term
First Claim
Patent Images

1. A dynamic circuit comprising:

  • a dynamic logic gate having an output node at which a logical output value of the logic gate is detected;

    a keeper circuit coupled to the output node, the keeper circuit including a feedback node; and

    a hardening capacitor coupled to the feedback node, the hardening capacitor to slow down a feedback path in the keeper circuit.

View all claims
  • 0 Assignments
Timeline View
Assignment View
    ×
    ×