Method and apparatus for reducing soft errors in dynamic circuits

• US 6,351,151 B2
• Filed: 07/18/2001
• Issued: 02/26/2002
• Est. Priority Date: 12/23/1999
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jiang, Wenjie, Kumar, Sudarshan
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): CHANG, DANIEL D
• Application Number:
  US09/909,104
• Publication Number:
  US 20010040467A1
• Time in Patent Office: 223 Days
• Field of Search: 326/95, 326/96, 326/97, 326/98, 257/297
• US Class Current: 326/98
• CPC Class Codes: H03K 19/00338 In field effect transistor circuits
• CPC Class Codes: H03K 19/096 Synchronous circuits, i.e. using clock signals H03K19/01728, H03K19/01855 take precedence

Abstract

A technique for reducing soft errors in a dynamic circuit. For one embodiment, a dynamic circuit includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected. A keeper circuit coupled to the output node is configured to harden the dynamic circuit by increasing the critical charge at the output node.

Claims

1. A dynamic circuit comprising:

a dynamic logic gate having an output node at which a logical output value of the logic gate is detected;

a keeper circuit coupled to the output node, the keeper circuit including a feedback node; and

a hardening capacitor coupled to the feedback node, the hardening capacitor to slow down a feedback path in the keeper circuit.

2. The dynamic circuit of claim 1 wherein the keeper circuit comprises:

a first inverter coupled between the output node and a feedback node, the first inverter being sized to reduce a driving strength of the inverter to slow down the feedback path in the keeper circuit.

3. The dynamic circuit of claim 2 wherein the keeper circuit further comprises:

a keeper device coupled to the first inverter, the keeper device being sized to further increase critical charge at the output node.

4. The circuit of claim 1 wherein the keeper circuit comprises:

a keeper device having an input coupled to the feedback node, the keeper device being sized to fight against changes in charge at the output node.

5. The circuit of claim 4 wherein

the dynamic logic gate is a domino gate, and

the keeper device is a PMOS keeper device.

6. The circuit of claim 4 wherein the keeper device is an NMOS keeper device.

7. The circuit of claim 4 wherein the keeper circuit further comprises:

an inverter coupled between the output node and the feedback node, the inverter being sized to reduce its driving strength to further harden the circuit.

8. The dynamic circuit of claim 1 wherein one terminal of the hardening capacitor is coupled to ground.

9. A method comprising:

using a hardening capacitor coupled to a feedback node of a keeper circuit in a dynamic circuit to slow down a feedback path in the keeper circuit to harden the dynamic circuit against soft errors.

10. The method of claim 9 further comprising:

further hardening the dynamic circuit with a keeper device that is sized to fight charge loss at an output node of the dynamic circuit.