Circuit and method for an integrated level shifting latch

• US 6,351,173 B1
• Filed: 08/25/2000
• Issued: 02/26/2002
• Est. Priority Date: 08/25/2000
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Ovens, Kevin M., Shinham, Thomas C.
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US09/648,721
• Time in Patent Office: 550 Days
• Field of Search: 327/333, 326/80, 326/81
• US Class Current: 327/333
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/01855 synchronous, i.e. using clock signals
• CPC Class Codes: H03K 3/356156 with synchronous operation
• CPC Class Codes: H03K 3/35625 using complementary field-effect transistors

Abstract

An integrated circuit (IC) comprising an integrated level shifting latch for I/O. The level shift in the IC I/O section may be clocked. In addition, a latch may be moved from the core section to the I/O section of the device, and thus the incoming clock may remain in the external voltage domain to clock the latch along with the level shift. The level shift and latch may be clocked on opposite phases of the clock. Preferably, the level shift and latch may operate differentially on the data signal. Both setup and clock-to-Q times are significantly reduced with respect to prior art devices, allowing higher speed industry specifications may be met.

Claims

1. An integrated circuit (IC) having a core section and an input/output (I/O) section, said IC comprising:

a clocked differential level shifter, wherein said differential level shifter receives differential data at a core voltage level and shifts the differential data from the core voltage level to an I/O voltage level to provide a differential data output at said I/O voltage level; and

a clocked latch coupled an output of said level shifter, wherein said latch captures said data at said I/O voltage level.

2. The integrated circuit of claim 1, wherein said latch is a differential input latch receiving said differential data output from said differential level shifter.

3. The integrated circuit of claim 2, wherein said latch provides a single-ended data output.

4. The integrated circuit of claim 1, wherein an external clock received by said IC remains at said I/O voltage level for clocking said level shifter and said latch.

5. The integrated circuit of claim 1, wherein said level shifter shifts said data on one phase of an external clock and said latch captures data on an opposite phase of said external clock.

6. The integrated circuit of claim 1, wherein said core voltage level is 1.8 volts and said I/O voltage level is 3.3 volts.

7. The integrated circuit of claim 1, wherein said latch is a master flip-flop of a master/slave flip-flop pair.

8. The integrated circuit of claim 1, wherein said level shifter comprises I/O voltage level transistors coupled to core voltage level transistors, wherein gates of said I/O voltage level transistors are coupled to a clock, and wherein gates of said core voltage level transistors are coupled to said core voltage level.

9. The integrated circuit of claim 1, wherein said IC is an application specific IC (ASIC).

10. A method of providing data at an output of an integrated circuit (IC), said IC comprising a core section having a core voltage level and an I/O section having an I/O voltage level, said method comprising:

level shifting said data differentially from said core voltage level to said I/O voltage level synchronous to an external clock; and

latching said data at said I/O voltage level synchronous to said external clock.

11. The method of claim 10, further comprising latching said data differentially.

12. The method of claim 11, further comprising providing a single-ended data signal to said output after said latching.

13. The method of claim 10, wherein said external clock remains at said I/O voltage level for synchronizing said level shifting and said latching.

14. The method of claim 10, further comprising level shifting said data on one phase of said external clock and latching said data on an opposite phase of said external clock.

15. The method of claim 10, wherein said core voltage level is 1.8 volts and said I/O voltage level is 3.3 volts.

16. An integrated circuit (IC) having a core section and an input/output (I/O) section, said IC comprising:

a clocked level shifter, wherein said level shifter shifts data from a core voltage level to an I/O voltage level, and further wherein said level shifter comprises I/O voltage level transistors coupled to core voltage level transistors, wherein gates of said I/O voltage level transistors are coupled to a clock, and wherein gates of said core voltage level transistors are coupled to said core voltage level; and

a clocked latch coupled an output of said level shifter, wherein said latch captures said data at said I/O voltage level.