Decision directed phase detector

• US 6,351,293 B1
• Filed: 07/13/1998
• Issued: 02/26/2002
• Est. Priority Date: 05/18/1998
• Status: Expired due to Term

• Current Assignee: AmTRAN Technology Co., Ltd., NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.), Sarnoff Corporation (SRI International, Inc.)
• Inventors: Perlow, Randall Bret
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): Yenke, Brian P.
• Application Number:
  US09/114,310
• Time in Patent Office: 1,324 Days
• Field of Search: H04/N.712, H04/N.5455, H04/N 1.102, H04/N 1.104, 348/432.1, 348/433.1, 348/436.1, 348/536, 348/539, 348/549, 348/726, 348/727, 375/321, 375/346, 455/204
• US Class Current: 348/726
• CPC Class Codes: H04L 27/066 Carrier recovery circuits H04L27/2271 takes precedence
• CPC Class Codes: H04L 7/027 extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
• CPC Class Codes: H04N 11/24 High-definition television systems
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 5/21 Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
• CPC Class Codes: H04N 5/455 Demodulation-circuits

Abstract

A decision directed phase detector that uses the quantized data output from a slicer to aid the phase error detection process to determine a phase error of a complex signal such as a vestigial sideband (VSB) signal containing in phase (I) and quadrature phase (Q) components (I and Q signals). The phase detector comprises subtractor having one input coupled to the I signal and a second input coupled to the data output of the slicer representing the magnitude of a sample point within a symbol. The quantized signal is subtracted from the I signal to produce ΔI signal. The Q signal is processed to determine its sign and magnitude. The sign and magnitude values are multiplied together and the result is multiplied with the ΔI signal to produce the phase error between the I and Q signals. This phase error signal is used in a digital television receiver to extract a data signal from a VSB signal for demodulation.

Claims

1. A decision directed phase detector for detecting the phase error of a vestigial sideband (VSB) signal comprising:

a subtractor having a first input coupled to an in-phase (I) signal and a second input coupled to a quantized I signal wherein the quantized I signal is subtracted from the I signal to produce a Δ

I signal;

a quadrature signal magnitude processing block having a quadrature phase (Q) signal as an input and having an output coupled to a first terminal of a first multiplier;

a quadrature signal sign processing block having said quadrature phase (Q) signal as an input and having an output coupled to a second terminal of the first multiplier, the output of the first multiplier being coupled to a second multiplier to multiply with the Δ

I signal to produce an error signal that represents a phase error of the VSB signal.

2. The decision directed phase detector of claim 1 wherein the quadrature signal magnitude processing block produces an n-th power absolute value of the Q signal, where n is an integer value.

3. The decision directed phase detector of claim 1 wherein said quadrature signal angle processing block produces the sign value of the Q signal.

4. A digital television receiver for demodulating a vestigial sideband (VSB) signal comprising:

a tuner for selecting a VSB signal from a plurality of VSB channels;

an analog-to-digital converter for digitizing the selected VSB signal at a sample rate established by an oscillator;

a complex Nyquist filter for extracting an in-phase (I) signal and a quadrature phase (Q) signal from the digitized VSB signal;

a complex equalizer for equalizing said I and Q signals;

a carrier recovery circuit for extracting I-data from the I signal;

wherein said carrier recovery circuit further comprises a phase tracking loop having a decision directed phase detector that uses both the I and Q signals for determining a phase error of the VSB signal.

5. The digital television receiver of claim 4 wherein said phase tracking loop comprises:

a complex multiplier for multiplying a phase adjusted oscillator signal with the I and Q signals to produce phase adjusted I and Q signals;

a slicer for quantizing the phase adjusted I signal to produce the I-data signal;

a decision directed phase detector for determining the phase error of the VSB signal using the I-data signal; and

a loop filter for filtering the phase error to produce the phase adjusted oscillator signal.

6. The digital television receiver of claim 5 wherein said decision directed phase detector comprises:

a subtractor having a first input coupled to the I signal and a second input coupled to I-data signal wherein the I-data signal is subtracted from the I signal to produce a Δ

I signal;

a quadrature signal magnitude processing block having the Q signal as an input and having an output coupled to a first terminal of a first multiplier;

a quadrature signal sign processing block having the Q signal as an input and having an output coupled to a second terminal of the first multiplier, the output of the first multiplier being coupled to a second multiplier to multiply with the Δ

I signal to produce an error signal that represents a phase error of the VSB signal.

7. The digital television receiver of claim 6 wherein said decision directed phase detector wherein the quadrature signal magnitude processing block produces an n-th power absolute value of the Q signal, where n is an integer value.

8. The digital television receiver of claim 6 wherein said quadrature signal angle processing block produces the sign value of the Q signal.

9. A method of determining a phase error of a vestigial sideband (VSB) signal having an in-phase (I) signal and a quadrature phase (Q) signal comprising the steps of:

subtracting a quantized I signal from the I signal to produce a Δ

I signal;

magnitude processing the Q signal to produce a magnitude value for the Q signal;

sign processing the Q signal to produce a sign value for the Q signal;

multiplying the magnitude value and the sign value to produce a first multiplied signal;

multiplying the first multiplied signal with the Δ

I signal to produce an error signal that represents a phase error of the VSB signal.

10. The method of claim 9 wherein the magnitude processing step produces an n-th power absolute value of the Q signal, where n is an integer value.

11. The method of claim 9 wherein said sign processing step produces the sign value of the Q signal.