Vertically stacked field programmable nonvolatile memory and method of fabrication

• US 6,351,406 B1
• Filed: 11/15/2000
• Issued: 02/26/2002
• Est. Priority Date: 11/16/1998
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Cleeves, James M., Subramanian, Vivek, Lee, Thomas H., Johnson, Mark G., Farmwald, P. Michael
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LE, THONG QUOC
• Application Number:
  US09/714,440
• Time in Patent Office: 468 Days
• Field of Search: 365/103, 365/174, 365/212, 365/230.06, 365/164
• US Class Current: 365/103
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode

Abstract

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Claims

1. A memory comprising:

a semiconductor substrate having peripheral circuits for the memory;

a memory array having a plurality of levels where each level includes a plurality of memory cells formed above the substrate, the memory cells at each level being coupled to a plurality of first and second lines; and

a plurality of vias for providing electrical connections between at least the first lines in more than one of the levels and the peripheral circuits of the substrate, each of the vias extending through more than one of the levels and contacting first lines in more than one level such that fewer than one via mask is needed per level.

2. The memory defined by claim 1 wherein the first and second lines are perpendicular to one another.

3. The memory defined by claim 2 wherein the substrate is silicon.

4. The memory defined by claim 2 or 3 wherein the vias are rectangular in shape.

5. The memory defined by claims 4 wherein the vias contain polysilicon.

6. The memory defined by claim 5 wherein the vias provide connections between the second lines more than one level and the peripheral circuits.

7. The memory defined by claim 1 wherein each memory cell comprising a diode and an antifuse.

8. The memory defined by claim 7 wherein one of the first and second lines in one of the plurality of layers makes electrical contact with a region of the same conductivity type of the diode in two of the levels of the memory array.

9. The memory defined by claim 8 wherein the vias have a rectangular cross section.

10. A memory comprising:

a semiconductor substrate; and

a plurality of separate three dimensional arrays of memory cells nestled with respect to one another on the substrate, each array comprising a plurality of levels of memory cells, the cells in each array communicating with peripheral circuits disposed in the substrate.

11. The memory defined by claim 10 wherein the peripheral circuits associated with each of the arrays has a layout having tabs at corners of the arrays.

12. The memory defined by claim 11 wherein the tabs are interdigitated.

13. The memory defined by claim 10 wherein each level has a plurality of first line and plurality of second lines generally perpendicular to the first lines, the first and second lines being connected to the cells.

14. The memory defined by claim 13 includes a plurality of vias for providing electrical connections between at least the first lines in the plurality of levels and the peripheral circuits of the substrate, each of the vias extending through more than one of the levels and contacting first lines in more than one level such that fewer than one via mask is needed per level.

15. The memory defined by claim 14 wherein the substrate is silicon.

16. A memory comprising:

a substrate;

a three dimensional memory array disposed on the substrate having a plurality of cells disposed in a plurality of levels;

the substrate including a plurality of decoders for accessing the cells with at least some of the decoders being folded under the array.

17. The memory defined by claim 16 wherein the decoders include both column decoders and row decoders with one of the column and row decoders being folded under the array in the substrate.

18. The memory defined by claim 17 wherein the plurality of cells disposed in a plurality of levels include a plurality of first and second lines.

19. The memory defined by claim 18 including a plurality of vias for providing electrical connections between at least the first lines in the plurality of levels and the decoders of the substrate, each of the vias extending through more than one of the levels and contacting first lines in more than one level such that fewer than one via mask is needed per level.

20. The memory defined by claim 18 or 19 wherein each cell of the memory array includes a diode and an antifuse.

21. The memory defined by claim 20 wherein the substrate is silicon.

22. A memory comprising:

a semiconductor substrate;

a memory array comprising a plurality of levels, each level having a plurality of column lines, a plurality of row lines and a plurality of memory cells, with a column line in a level n also being a column line in a level n+1 and a row line in level n also being a row line in level n−

1;

the substrate containing column decoders and row decoders coupled to the column and row lines, respectively, with at least a part of one of the row and column decoders being disposed under the array.

23. The memory defined by claim 22 wherein the substrate includes circuits for sensing the state of the cells in a current mode.

24. The memory defined by claim 22 including a plurality of vias for providing electrical connections between at least the column lines in the plurality of levels and the decoders of the substrate, each of the vias extending through more than one of the levels and contacting column lines in more than one level such that fewer than one via mask is needed per level.

25. The memory defined by claim 24 wherein the substrate is silicon.

26. The memory defined by claim 25 wherein each memory cell comprises a diode and an antifuse.