Non-volatile semiconductor memory device having a function for controlling the range of distribution of memory cell threshold voltages and method of erasing data thereof

• US 6,351,417 B1
• Filed: 04/13/2001
• Issued: 02/26/2002
• Est. Priority Date: 12/25/1998
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tanzawa, Toru, Shiga, Hitoshi, Saito, Masanobu
• Primary Examiner(s): Tran, Andrew Q.
• Application Number:
  US09/833,687
• Time in Patent Office: 319 Days
• Field of Search: 365/185.22, 365/185.2, 365/185.19, 365/185.11, 365/185.29, 365/185.33
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3409 Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
• CPC Class Codes: G11C 2216/20 Suspension of programming or erasing cells in an array in order to read other cells in it

Abstract

A non-volatile semiconductor memory device according to the invention comprises a memory cell array having a plurality of non-volatile memory cells, and a write state machine controlling a voltage applied to a memory cell selected from the memory cell array and a voltage application period, in accordance with each of reading of data from the selected memory cell, writing of data into the selected memory cell, and erasing of data from the selected memory. The write state machine executes writing, under a first writing condition, on a predetermined number of memory cells included in the memory cell array, and executes writing on memory cells other than the predetermined number of memory cells, under a second writing condition set in accordance with a result of the writing executed under the first writing condition.

Claims

1. A method of erasing data for a non-volatile semiconductor memory device, comprising:

counting a first number of writing operations executed on each memory cell of a first group;

generating a first signal indicating an increase in writing voltage applied to each memory cell of a second group not part of said first group, on the basis of said first number of writing operations, and a second number of writing operations executed on said each memory cell of said second group, and controlling said first signal indicating the increase in writing voltage by feeding back said first signal to an input side; and

generating a writing voltage applied to said each memory cell of said second group on the basis of said first signal and a second signal indicating a writing voltage applied to said each memory cell of said first group.

2. The method of erasing data for a non-volatile semiconductor memory device according to claim 1, wherein said first group includes a plurality of dummy cells.

3. The method of erasing data for a non-volatile semiconductor memory device according to claim 1, wherein said writing operation executed on each memory cell of said first group includes writing and verification of writing executed on each memory cell, said verification of writing being a reading operation for verifying whether or not data written during writing is kept as desired data.

4. The method of erasing data for a non-volatile semiconductor memory device according to claim 1, wherein said writing operation executed on each memory cell of said first group includes writing and verification of writing executed on each memory cell, and said writing operation on each memory cell of said second group includes writing and verification of writing executed on each memory cell, said verification of writing being a reading operation for verifying whether or not data written during writing is kept as desired data.

5. The method of erasing data for a non-volatile semiconductor memory device according to claim 1, wherein said writing operation includes an erasing operation for erasing data.

6. The method of erasing data for a non-volatile semiconductor memory device according to claim 1, wherein said writing voltage applied to each memory cell of said second group is increased each time said writing on said each memory cell of said second group is repeated.

7. A method of erasing data for a non-volatile semiconductor memory device including a memory cell array having a plurality of non-volatile memory cells which is divided into a plurality of blocks comprising:

erasing data simultaneously from said plurality of blocks, each block including a plurality of dummy cells;

counting a first number of writing operations executed on each dummy cell;

generating a first signal indicating an increase in writing voltage applied to each memory cell, other than said dummy cells, in each of said blocks on the basis of said first number of writing operations and a second number of writing operations executed on each memory cell, other than said dummy cells, in each of said blocks, and controlling said first signal indicating the increase in writing voltage by feeding back said first signal to an input side; and

generating a writing voltage applied to each memory cell, other than said dummy cells, in each of said blocks on the basis of said first signal and a second signal indicating a writing voltage applied to each of said dummy cells.

8. A method of erasing data for a non-volatile semiconductor memory device, comprising:

erasing data from each of a plurality of memory cells divided into first and second groups;

setting a first writing condition by a writing voltage and a writing voltage application period applied to each memory cell in said first group;

verifying whether or not data stored in each memory cell of said first group is desired, executing writing on each memory cell under said first writing condition, if the data is not desired, repeating the writing and the verification until the data stored in each memory cell of said first group becomes desired, and counting a first number of writing operations executed on each memory cell of said first group until the data becomes desired;

generating a first signal indicating an increase in writing voltage applied to each memory cell of said second group on the basis of said first number of writing operations and a second number of writing operations executed on each memory cell of said second group, and controlling said first signal indicating the increase in writing voltage by feeding back said first signal indicating the increase in writing voltage to an input side;

generating a writing voltage applied to each memory cell of said second group on the basis of said first signal and a second signal indicating a writing voltage applied to each memory cell of said first group;

setting a second writing condition by said writing voltage and a writing voltage application period applied to each memory cell in said second group; and

verifying whether or not data stored in each memory cell of said second group is desired, executing writing on each memory cell under said second writing condition, if the data is not desired, repeating the writing and the verification until the data stored in each memory cell in said second group becomes desired.