Binary to binary-encoded-ternary (BET) decoder using reordered logic

• US 6,351,429 B1
• Filed: 06/29/2000
• Issued: 02/26/2002
• Est. Priority Date: 06/29/2000
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ross, John M., Netis, Dmitry, Hsu, Louis L.
• Primary Examiner(s): Le, Vu A.
• Assistant Examiner(s): PHUNG, ANH K
• Application Number:
  US09/607,097
• Time in Patent Office: 607 Days
• Field of Search: 365/230.06, 365/168, 365/49, 365/230.04, 365/230.01
• US Class Current: 365/230.06
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 8/10 Decoders

Abstract

An integrated circuit memory device comprising an arrangement of physical wordlines, WL0-WLn, arrange such that each wordline is addressed by a plurality of pairs, An+1, An, of logical row address bits, and such that at least one pair of logical row address bits, corresponding to physically adjacent wordlines Wlm, Wlm+1, Wlm+2 in succession, cycles between binary states which encode the ternary results A, B and C in succession. The ternary results A, B or C are used to determine which two bitlines of a possible three bitlines are selected by a multiplexer which connects the bitlines to a sense amplifier for determining the state of a bit stored in a memory cell accessed by an activated wordline and a selected bitline. Preferably, the ternary results A, B and C are respectively encoded by said binary states of said pair of logical row address bits, said binary states being “00,” “01,” and “10” respectively.

Claims

1. An integrated circuit memory device comprising:

an arrangement of physical wordlines, WL0-WLn, arranged such that each wordline is addressed by a plurality of pairs, An+1, An, of logical row address bits, such that at least one pair of logical row address bits, corresponding to physically adjacent wordlines Wlm, Wlm+1, Wlm+2 in succession, cycles between binary states which encode the ternary results A, B and C in succession; and

further wherein the ternary results A, B or C are used to determine which two bitlines of a possible three bitlines are selected by a multiplexer which connects the bitlines to a sense amplifier for determining the state of a bit stored in a memory cell accessed by an activated wordline and a selected bitline.

2. The integrated circuit memory device of claim 1, wherein said ternary results A, B and C are respectively encoded by said binary states of said pair of logical row address bits, said binary states being “

00 ,”

“

01 ,” and

“

10”

respectively.

3. The integrated circuit memory device of claim 1, wherein, for different groups of the wordlines, different pairs of logical row address bits cycle between the binary states that encode the ternary results A, B and C in succession.

4. The integrated circuit memory device of claim 3, further including a logic block for identifying, from the address bits of the wordlines, the pair of bits of the addresses that cycle between said binary states.

5. A method of managing an integrated circuit memory device having a multitude of wordlines, WL0-WLn, arranged in a given physical order, the method comprising the steps:

addressing the wordlines such that each wordline is addressed by a plurality of pairs, An+1, An, of logical row address bits, such that at least one pair of logical row address bits, corresponding to physically adjacent wordlines Wlm, Wlm+1, Wlm+2 in succession, cycles between binary states which encode the ternary results A, B and C in succession; and

using the ternary results to determine which two bitlines of a possible three bitlines are selected by a multiplexer which connects the bitlines to a sense amplifier for determining the state of a bit stored in a memory cell accessed by an activated wordline and a selected bitline.

6. A method according to claim 5, wherein said ternary results A, B and C are respectively encoded by said binary states of said pair of logical row address bits, said binary states being “

00 ,”

“

01 ,” and

“

10”

respectively.

7. A method according to claim 5, wherein, for different groups of the wordlines, different pairs of logical row address bits cycle between the binary states that encode the ternary results A, B and C in succession.

8. A method according to claim 7, further including the step of using a logic block for identifying, from the address bits of the wordlines, the pair of bits of the addresses that cycle between said binary states.

9. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for managing an integrated circuit memory device having a multitude of wordlines, WL0-WLn, arranged in a given physical order, said method steps comprising:

addressing the wordlines such that each wordline is addressed by a plurality of pairs, An+1, An, of logical row address bits, such that at least one pair of logical row address bits, corresponding to physically adjacent wordlines Wlm, Wlm+1, Wlm+2 in succession, cycles between binary states which encode the ternary results A, B and C in succession; and

using the ternary results to determine which two bitlines of a possible three bitlines are selected by a multiplexer which connects the bitlines to a sense amplifier for determining the state of a bit stored in a memory cell accessed by an activated wordline and a selected bitline.

10. A program storage device according to claim 9, wherein said ternary results A, B and C are respectively encoded by said binary states of said pair of logical row address bits, said binary states being “

00 ,”

“

01 ,” and

“

10”

respectively.

11. A program storage device according to claim 9, wherein, for different groups of the wordlines, different pairs of logical row address bits cycle between the binary states that encode the ternary results A, B and C in succession.

12. A program storage device according to claim 11, wherein said method steps further include the step of using a logic block for identifying, from the address bits of the wordlines, the pair of bits of the addresses that cycle between said binary states.