Binary to binary-encoded-ternary (BET) decoder using reordered logic
First Claim
1. An integrated circuit memory device comprising:
- an arrangement of physical wordlines, WL0-WLn, arranged such that each wordline is addressed by a plurality of pairs, An+1, An, of logical row address bits, such that at least one pair of logical row address bits, corresponding to physically adjacent wordlines Wlm, Wlm+1, Wlm+2 in succession, cycles between binary states which encode the ternary results A, B and C in succession; and
further wherein the ternary results A, B or C are used to determine which two bitlines of a possible three bitlines are selected by a multiplexer which connects the bitlines to a sense amplifier for determining the state of a bit stored in a memory cell accessed by an activated wordline and a selected bitline.
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Accused Products
Abstract
An integrated circuit memory device comprising an arrangement of physical wordlines, WL0-WLn, arrange such that each wordline is addressed by a plurality of pairs, An+1, An, of logical row address bits, and such that at least one pair of logical row address bits, corresponding to physically adjacent wordlines Wlm, Wlm+1, Wlm+2 in succession, cycles between binary states which encode the ternary results A, B and C in succession. The ternary results A, B or C are used to determine which two bitlines of a possible three bitlines are selected by a multiplexer which connects the bitlines to a sense amplifier for determining the state of a bit stored in a memory cell accessed by an activated wordline and a selected bitline. Preferably, the ternary results A, B and C are respectively encoded by said binary states of said pair of logical row address bits, said binary states being “00,” “01,” and “10” respectively.
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Citations
12 Claims
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1. An integrated circuit memory device comprising:
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an arrangement of physical wordlines, WL0-WLn, arranged such that each wordline is addressed by a plurality of pairs, An+1, An, of logical row address bits, such that at least one pair of logical row address bits, corresponding to physically adjacent wordlines Wlm, Wlm+1, Wlm+2 in succession, cycles between binary states which encode the ternary results A, B and C in succession; and
further wherein the ternary results A, B or C are used to determine which two bitlines of a possible three bitlines are selected by a multiplexer which connects the bitlines to a sense amplifier for determining the state of a bit stored in a memory cell accessed by an activated wordline and a selected bitline. - View Dependent Claims (2, 3, 4)
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5. A method of managing an integrated circuit memory device having a multitude of wordlines, WL0-WLn, arranged in a given physical order, the method comprising the steps:
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addressing the wordlines such that each wordline is addressed by a plurality of pairs, An+1, An, of logical row address bits, such that at least one pair of logical row address bits, corresponding to physically adjacent wordlines Wlm, Wlm+1, Wlm+2 in succession, cycles between binary states which encode the ternary results A, B and C in succession; and
using the ternary results to determine which two bitlines of a possible three bitlines are selected by a multiplexer which connects the bitlines to a sense amplifier for determining the state of a bit stored in a memory cell accessed by an activated wordline and a selected bitline. - View Dependent Claims (6, 7, 8)
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9. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for managing an integrated circuit memory device having a multitude of wordlines, WL0-WLn, arranged in a given physical order, said method steps comprising:
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addressing the wordlines such that each wordline is addressed by a plurality of pairs, An+1, An, of logical row address bits, such that at least one pair of logical row address bits, corresponding to physically adjacent wordlines Wlm, Wlm+1, Wlm+2 in succession, cycles between binary states which encode the ternary results A, B and C in succession; and
using the ternary results to determine which two bitlines of a possible three bitlines are selected by a multiplexer which connects the bitlines to a sense amplifier for determining the state of a bit stored in a memory cell accessed by an activated wordline and a selected bitline. - View Dependent Claims (10, 11, 12)
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Specification