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Binary to binary-encoded-ternary (BET) decoder using reordered logic

  • US 6,351,429 B1
  • Filed: 06/29/2000
  • Issued: 02/26/2002
  • Est. Priority Date: 06/29/2000
  • Status: Expired due to Term
First Claim
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1. An integrated circuit memory device comprising:

  • an arrangement of physical wordlines, WL0-WLn, arranged such that each wordline is addressed by a plurality of pairs, An+1, An, of logical row address bits, such that at least one pair of logical row address bits, corresponding to physically adjacent wordlines Wlm, Wlm+1, Wlm+2 in succession, cycles between binary states which encode the ternary results A, B and C in succession; and

    further wherein the ternary results A, B or C are used to determine which two bitlines of a possible three bitlines are selected by a multiplexer which connects the bitlines to a sense amplifier for determining the state of a bit stored in a memory cell accessed by an activated wordline and a selected bitline.

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