Method and apparatus for reducing power consumption of digital subscriber line modems

• US 6,351,509 B1
• Filed: 12/23/1999
• Issued: 02/26/2002
• Est. Priority Date: 12/23/1999
• Status: Expired due to Term

• Current Assignee: STMicroelectronics NV
• Original Assignee: Tikcro Technologies Ltd.
• Inventors: Vitenberg, Roman, Koren, Victor, Frenkel, Liron
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): LIU, SHUWANG
• Application Number:
  US09/471,895
• Time in Patent Office: 796 Days
• Field of Search: 375/222, 375/377, 375/229, 375/285, 375/260, 375/295, 375/219, 330/297, 326/83
• US Class Current: 375/377
• CPC Class Codes: H04L 27/0002 analog front ends; means for connecting modulators, demodulators or transceivers to a transmission line duplex arrangements H04L5/143
• CPC Class Codes: H04L 27/2614 Peak power aspects
• CPC Class Codes: H04L 27/2626 Arrangements specific to the transmitter only
• CPC Class Codes: H04L 5/023 Multiplexing of multicarrier modulation signals multicarrier modulation H04L27/2601

Abstract

A system and method is presented for reducing the power consumed by a line driver driving a signal to be transmitted through a communications media. The preferred method includes the steps of: (1) delaying the signal; (2) determining whether the signal has reached a predetermined threshold value; (3) increasing power supplied to the line driver in response to an indication from the determining step that the threshold has been reached; and (4) delivering the delayed signal to the line driver. The preferred system includes: (1) a digital signal processor; (2) a line driver; (3) a digital delay line disposed between the digital signal processor and the line driver; and (4) a power regulator disposed between the threshold detector and the line driver. The system and method, while applicable to many communications formats, is particularly applicable to communications methods transmitting signals having a relatively large dynamic range, such as xDSL communications techniques.

Claims

1. A method for reducing the power consumed by a line driver driving a signal to be transmitted through a communications medium comprising the steps of:

(a) delaying said signal to produce a delayed signal;

(b) determining whether said signal has reached a predetermined threshold value;

(c) increasing power supplied to said line driver in response to said signal reaching said predetermined threshold value;

(d) delivering said delayed signal to said line driver; and

(e) reducing power supplied to said line driver after a predetermined time interval.

2. The method of claim 1, wherein said threshold value is between an root mean square RMS and a peak value of said signal.

3. The method of claim 1, wherein said delaying and said determining step commence substantially contemporaneously.

4. The method of claim 1, wherein said signal is delayed for a time period approximately equal to a time necessary to complete said determining and said increasing step.

5. The method of claim 1, wherein said determining step includes the steps of:

(a) filtering and interpolating said signal; and

(b) comparing said signal to said predetermined threshold value.

6. The method of claim 1, wherein said signal is a discrete multitone signal.

7. The method of claim 1, including the additional steps of:

(f) producing a leakage error correction signal based on said power supplied to said line driver; and

(g) subtracting said correction signal from said signal to be transmitted.

8. The method of claim 7, including the further steps of:

(h) transmitting said delayed signal over a communications medium;

(i) receiving from said communications medium an echo signal of said transmitted signal;

(j) producing an echo response signal of said signal to be transmitted;

(k) producing a residual signal based on said received signal of step (i) and said produced signal of step (j); and

(l) adjusting said leakage error correcting signal produced at step (f) based on said residual signal produced at step (k).

9. The method of claim 1, including the additional steps of:

(f) zeroing said signal to be transmitted;

(g) increasing power supplied to said line driver;

(h) receiving an echo signal from said communications media caused by said increased power of step (g);

(i) producing a correction signal based on said echo signal of step (h); and

(j) subtracting said correction signal of step (i) from said signal to be transmitted.

10. A method for reducing the power consumed by a plurality of line drivers, each driving a respective signal to be transmitted through a respective communications medium, comprising the steps of:

(a) delaying each of said plurality of signals to produce a corresponding plurality of delayed signals;

(b) determining whether any of said plurality of signals has reached a predetermined threshold value;

(c) increasing power supplied to each of said line drivers in response to at least one of said plurality of signals reaching said predetermined threshold value; and

(d) delivering each of said plurality of delayed signals to each of said line drivers;

(e) reducing power supplied to each of said line drivers after a predetermined time interval.

11. The method of claim 10, wherein said delaying and said determining steps commence substantially contemporaneously.

12. A system for driving a discrete multitone signal over a communications medium comprising:

(a) a digital signal processor having a signal output;

(b) a line driver having a signal input, a signal output and one or more power inputs;

(c) a power regulator having a control input, one or more power inputs and a plurality of power outputs;

(d) a digital delay line disposed between the output of said digital signal processor and said signal input of said line driver;

(e) a threshold detector disposed between said output of said digital signal processor and said control input of said power regulator;

(f) a power supply having one or more powers outputs respectively connected to said one or more power inputs of said power regulator;

(g) a digital-to-analog converter disposed between an output of said digital delay line and the signal input of said line driver;

(h) a transformer having a signal input and a signal output, said signal input being connected to said signal output of said line driver.

13. The system of claim 12, wherein said digital delay line is implemented in RAM memory.

14. The system of claim 12, wherein said digital delay line is implemented by a filter.

15. The system of claim 12, wherein said digital delay line and said threshold detector are implemented in said digital signal processor.

16. The system of claim 12, wherein said threshold detector includes a preliminary stage compensating filter.

17. The system of claim 12, wherein said digital-to-analog converter is implemented in said digital signal processor.

18. The system of claim 12, wherein said power supply comprises a high power supply and a low power supply.

19. The system of claim 12, wherein said power regulator comprises:

(a) a low pass filter having a signal input, a signal output and one or more power inputs;

(b) an amplifier having a signal input, a signal output and one or more power inputs, said signal input coupled to said signal output of said low pass filter;

(c) an inverter having a signal input, a signal output and one or more power inputs, said signal input coupled to the signal output of said amplifier;

(d) a first and second transistor configured push-pull stage, each having a signal input, a signal output and one or more power inputs;

the signal input of said first transistor configured push-pull stage coupled to the signal output of said amplifier and the signal input of said second transistor configured push-pull stage coupled to the signal output of said amplifier; and

(e) said one or more outputs of said power supply connected to said one or more power inputs of said low pass filter;

said amplifier, said inverter and said transistor configured push-pull stages.

20. The system of claim 12, wherein said power regulator comprises:

(a) a switch having 4 input terminals and 2 output terminals, each of said input terminals being connected to one of said power supply power outputs;

said power supply power outputs including;

a positive high power supply connected to a first of said input terminals;

a negative high power supply connected to a second of said input terminals;

a positive low power supply connected to a third of said input terminals; and

a negative low power supply connected to a fourth of said input terminals.

21. The system of claim 12, wherein said power regulator further comprises a switched capacitor selectively connectable to a power supply output of a first polarity for selectively increasing the voltage output of said power source when said threshold detector is in a high power state.

22. The system of claim 21, wherein said power regulator is further selectively connectable to ground for selectably decreasing the voltage output of said power source when said threshold detector is in a low power state.

23. The system of claim 21, wherein said power regulator is further selectively connectable to a power supply of a polarity opposite that of said first polarity for selectively decreasing the voltage output of said power source when said detector is in a low power state.

24. The system of claim 12, further including:

(i) a supply leakage canceller having a signal input and a signal output, said signal input receiving a signal from said threshold detector and said signal output being subtracted from the signal output by said digital delay line.

25. The system of claim 24, further including:

(j) a hybrid circuit having a signal output, a signal input and a signal feed back output, said signal input connected to said signal output of said line driver;

(k) an echo canceller having a signal input and a signal output, said signal input connected to the signal output of said digital signal processor;

(l) an analog to digital converter, said analog to digital converter having a signal input and a signal output, said signal input connected to the signal feedback output of said hybrid circuit and said signal output connected to the signal output of said echo canceller, said signal output of said echo canceller being subtracted from the signal output of said analog to digital converter to form a residual echo signal output;

(m) said supply leakage canceller having a feed back signal input, said feed back signal input connected to said residual echo signal output.

26. A system for driving a discrete multitone signal over a communications media comprising:

(a) a digital signal processor, said digital signal processor outputting said discrete multitone signal at a signal output of said digital signal processor;

(b) a digital delay line coupled to the signal output of said digital signal processor and to the input of a digital-to-analog converter, said digital delay line receiving said discrete multitone signal in digital form from said digital signal processor and delivering a delayed version of said digital signal to said digital-to-analog converter;

(c) said digital-to-analog converter receiving the delayed version of said digital signal and delivering an analog version of the digital signal to a line driver;

(d) a threshold detector coupled to the signal output of said digital signal processor and a control input of a power regulator, said threshold detector receiving said discrete multitone signal from said digital signal processor and delivering to the control input of said regulator an indication signal indicating whether said discrete multitone signal has reached said threshold value;

(e) said power regulator coupled to a power supply and to one or more power inputs of said line driver, said power regulator normally providing said line driver with a low power source and upon receiving at said control input said indication signal from said threshold detector, supplying said line driver with a high power source; and

(f) said line driver coupled to said power regulator and to an output of said digital to analog converter, said line driver driving said analog discrete multitone signal at a power determined by said indication signal;

(g) a transformer having a signal input, said signal input coupled to a signal output of said line driver.

27. A system for driving a signal over a communications medium, comprising:

(a) means for producing said signal;

(b) means for detecting and indicating whether said signal has reached a predetermined threshold;

(c) means for providing a power source that produces, for a predetermined time interval, an increased power level in response to said indication from said detecting means;

(d) means for delaying said signal;

(e) means for driving said signal using said power source means; and

(f) means for delivering said delayed signal to said driving means.

28. The system of claim 27 further comprising:

(g) means for producing a leakage error correction signal based on said power source means; and

(h) means for subtracting said correction signal from said signal.

29. The system of claim 27, further comprising:

(g) means for receiving from said communications medium an echo of said driven signal;

(h) means for reproducing an echo response signal of said signals;

(i) means for producing a residual signal;

(j) means for adjusting said leakage error correcting signal based on said residual signal.