Method and apparatus for a multi-chip module that is testable and reconfigurable based on testing results

• US 6,351,681 B1
• Filed: 11/23/1998
• Issued: 02/26/2002
• Est. Priority Date: 05/09/1997
• Status: Expired due to Term

• Current Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: ATI International SRL (Advanced Micro Devices, Inc.)
• Inventors: Lee, Keith S. K., Lau, Lee K., Chih, David
• Primary Examiner(s): Gordon, Paul P.
• Application Number:
  US09/197,720
• Time in Patent Office: 1,191 Days
• Field of Search: 700/121, 711/2, 711/129, 711/170, 711/171, 324/755, 324/756, 324/758, 324/760, 324/765
• US Class Current: 700/121
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318513 Test of Multi-Chip-Moduls
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

A method and apparatus for a multi-chip module that is testable and reconfigurable based on testing results is accomplished by a multi-chip module that includes a first circuit disposed on a first chip substrate, a second circuit disposed on second chip substrate, and an interconnecting substrate operably coupled to the first chip substrate and the second chip substrate. The interconnecting substrate connects the first circuit to the second circuit. The interconnecting substrate includes external connectors for accessing signals within the multi-chip module, which allow the multi-chip module to be fully tested. This testing may include isolating the first circuit and/or the second circuit by disabling other circuits in order to allow each of the circuits to be exercised without interference from other circuits. After testing the multi-chip module, configuration circuitry included on the multi-chip module may be used to reconfigure the multi-chip module based on results of the testing.

Claims

1. A video graphics multi-chip module comprising:

a video graphics circuit disposed on a first chip substrate;

a memory circuit disposed on a second chip substrate; and

an interconnecting substrate operably coupled to the first chip substrate and the second chip substrate, wherein the interconnecting substrate electrically couples the video graphics circuit to the memory circuit, and wherein the interconnecting substrate includes external connectors for accessing signals within the video graphics multi-chip module.

2. The video graphics multi-chip module of claim 1,

wherein the video graphics circuit further comprises a first control signal output for controlling the memory circuit, wherein the first control signal output is coupled to a first external connector of the interconnecting substrate;

wherein the memory circuit further comprises a first control signal input for controlling the memory circuit, wherein the first control signal input is coupled to a second external connector of the interconnecting substrate;

wherein when the video graphics multi-chip module is in a testing mode, input to the first control signal input is provided via the second external connector and output from the first output control signal is received via the first external connector; and

wherein when the video graphics multi-chip module is in an operational mode, the first external connector is coupled to the second external connector such that the first control signal output of the video graphics circuit drives the first control signal input of the memory.

3. The video graphics circuit of claim 2 further comprises a signal conditioning block operably coupled to the first external connector and second external connectors of the interconnecting substrate, wherein when the video graphics multi-chip module is in the operational mode, the signal conditioning block ensures signal integrity of the first control signal input.

4. The video graphics multi-chip module of claim 1,

wherein the video graphics circuit further comprises a plurality of control signal outputs for controlling the memory circuit, wherein each of the plurality of control signal outputs is coupled to a corresponding one of a first set of external connectors of the interconnecting substrate;

wherein the memory circuit further comprises a plurality of control signal inputs for controlling the memory circuit, wherein each of the plurality of control signal inputs is coupled to a corresponding one of a second set of external connectors of the interconnecting substrate;

wherein when the video graphics multi-chip module is in a testing mode, input to the plurality of control signal inputs is provided via the second set of external connectors and output from the plurality of control signal outputs is received via the first set of external connectors; and

wherein when the video graphics multi-chip module is in an operational mode, each one of the first set of external connectors is coupled to a corresponding one of the second set of external connectors such that each of the plurality of control signal outputs drives a corresponding one of the plurality of control signal inputs.

5. The video graphics multi-chip module of claim 4 wherein the plurality of control signal outputs includes a clock output, a chip select output, and a clock enable output, and wherein the plurality of control signal inputs include a clock input, a chip select input, and a clock enable input.

6. The video graphics circuit of claim 5 further comprises a signal conditioning block operably coupled to at least one of the first set of external connectors and at least one of the second set of external connectors of the interconnecting substrate, wherein when the video graphics multi-chip module is in the operational mode, the signal conditioning block ensures signal integrity of at least one of the plurality of control signal inputs.

7. The video graphics circuit of claim 6, wherein the signal conditioning block ensures signal integrity of at least the clock input.

8. The video graphics multi-chip module of claim 5, wherein when a first set of signals is applied to the plurality of control signal inputs, the memory circuit is disabled such that the video graphics circuit can be tested without interference from the memory circuit.

9. The video graphics multi-chip module of the claim 8, wherein when the first set of signals is applied to the plurality of control signal inputs, the outputs of the memory circuit are tri-stated.

10. The video graphics multi-chip module of claim 9, wherein the first set of signals is generated by a tester external to the video graphics multi-chip module.

11. The video graphics multi-chip module of claim 1, wherein the video graphics circuit includes a video graphics circuit control input, wherein the video graphics circuit control input is coupled to an external connector of the interconnecting substrate, wherein when the video graphics circuit control input is asserted, the video graphics circuit is disabled.

12. The video graphics multi-chip module of claim 1, wherein the interconnecting substrate is a four-layer substrate, wherein each layer of the substrate is composed of conducting material for use in coupling the video graphics circuit to the memory circuit.

13. The video graphics multi-hip module of claim 1, wherein the external connectors of the interconnecting substrate are bump connectors of a bump grid array.

14. The video graphics multi-chip module of claim 1 further comprises configuration circuitry operably coupled to the video graphics circuit and the memory circuit, and wherein the configuration circuitry configures the video graphics multi-chip module based on the functional status of the video graphics circuit and the memory circuit.

15. The video graphics multi-chip module of claim 14, wherein the configuration circuitry configures the video graphics multi-chip module to use only the video graphics circuit when the memory circuit failed the testing.

16. The video graphics multi-chip module of claim 14, wherein the configuration circuitry configures the video graphics multi-chip module to use only the memory circuit when the video graphics circuit failed the testing.

17. The video graphics multi-chip module of claim 1 further comprises a second memory circuit disposed on a third chip substrate, wherein the interconnecting substrate operably couples the second memory circuit to the video graphics circuit.

18. A method for manufacturing a multi-chip module, the method comprising:

depositing a first circuit on a first die;

depositing a second circuit on a second die;

mounting the first die and the second die to an interconnecting substrate, wherein the interconnecting substrate electrically couples the first die and the second die;

testing the first circuit and the second circuit;

packaging the interconnecting substrate including the first die and the second die, wherein the packaging is based on the testing.

19. The method of claim 18, wherein the first circuit includes a video graphics circuit and the second circuit includes a memory.

20. The method of claim 18, wherein packaging further comprises packaging the interconnecting substrate such that only portions of the multi-chip module which pass testing are functionally packaged.

21. A method for testing a multi-chip module comprising:

applying a first plurality of inputs to externally accessible ports of the multi-chip module, wherein the first plurality of inputs disables outputs of a first circuit of the multi-chip module, wherein the multi-chip module includes;

the first circuit disposed on a first chip substrate

a second circuit disposed on a second chip substrate;

an interconnecting substrate, wherein the interconnecting substrate includes;

a first set of connectors coupling the first circuit to the second circuit;

a second set of connectors coupling control signals of the first circuit to a first portion of the externally accessible ports of the multi-chip module; and

a third set of connectors coupling control signals of the second circuit to a second portion of the externally accessible ports of the multi-chip module;

applying a second plurality of inputs to the externally accessible ports of the multi-chip module, wherein the second circuit of the multi-chip module produces a first plurality of outputs in response to the second plurality of inputs; and

comparing the first plurality of outputs to a first plurality of expected values to determine if the second circuit is functioning correctly.

22. The method of claim 21 further comprises:

applying a third plurality of inputs to the externally accessible ports of the multi-chip module, wherein the third plurality of inputs disables outputs of the second circuit of the multi-chip module;

applying a fourth plurality of inputs to the externally accessible ports of the multi-chip module, wherein the first circuit of the multi-chip module produces a second plurality of outputs in response to the fourth plurality of inputs; and

comparing the second plurality of outputs to a second plurality of expected values to determine if the first circuit is functioning correctly.

23. The method of claim 22 further comprises configuring the multi-chip module such that circuits of the multi-chip module that are not functioning correctly are disabled.

24. The method of claim 21, wherein the first circuit includes a memory circuit and the second circuit includes a video graphics circuit.

25. A multi-chip module comprising:

an interconnecting substrate, wherein the interconnecting substrate includes a set of externally accessible ports;

a first circuit disposed on a first die, wherein the first die is mounted to the interconnecting substrate;

a second circuit disposed on a second die, wherein the second die is mounted to the interconnecting substrate; and

configuration circuitry operably coupled to the interconnecting substrate, the first circuit, and the second circuit, wherein in an operational mode;

the configuration circuitry operably couples a first set of signals of the first circuit to a first set of signals of the second circuit, and the configuration circuitry operably couples the set of externally accessible ports to a second set of signals of the first circuit; and

wherein in a testing mode the configuration circuitry switches the connectivity of the externally accessible ports based on control signals.

26. The multi-chip module of claim 25, wherein when the configuration circuitry receives control signals including a first circuit test configuration sequence, the configuration circuitry couples the externally accessible ports to the first set of signals of the first circuit.

27. The multi-chip module of claim 26, wherein when the configuration circuitry receives control signals including a first circuit test configuration sequence, the configuration circuitry disables the second circuit.

28. The multi-chip module of claim 25, wherein when the configuration circuitry receives control signals including a second circuit test configuration sequence, the configuration circuitry couples the externally accessible ports to the first set of signals of the second circuit.

29. The multi-chip module of claim 28, wherein when the configuration circuitry receives control signals including a second circuit test configuration sequence, the configuration circuitry disables the first circuit.

30. The multi-chip module of claim 25, wherein the first circuit includes a graphics processor, the second circuit includes a first memory, and wherein the set of externally accessible ports are adapted to couple to a second memory.

31. A method for testing a multi-chip module, wherein the multi-chip module includes a first circuit, a second circuit, and a set of externally accessible ports, wherein in an operational mode, a first set of signals of the first circuit is coupled to a first set of signals of the second circuit, and the set of externally accessible ports is operably coupled to a second set of signals of the first circuit, the method comprising:

receiving a test sequence, wherein coupling within the multi-chip module is altered based on the test sequence,

wherein when the test sequence indicates a first circuit test, the set of externally accessible ports is coupled to the first set of signals of the first circuit,

wherein when the test sequence indicates a second circuit test, the set of externally accessible ports is coupled to the first set of signals of the second circuit;

applying test vectors to the multi-chip module; and

comparing results of the test vectors with expected values to determine functionality of at least a portion of the multi-chip module.

32. The method of claim 31, wherein receiving further comprises:

when the test sequence indicates a first circuit test, disabling the second circuit, and

when the test sequence indicates a second circuit test, disabling the first circuit.