Voltage and clock margin testing of memory-modules using an adapter board mounted to a PC motherboard

• US 6,351,827 B1
• Filed: 10/30/2000
• Issued: 02/26/2002
• Est. Priority Date: 04/08/1998
• Status: Expired due to Term

• Current Assignee: Kingston Technology Company (Kingston Technology Corporation)
• Original Assignee: Kingston Technology Company (Kingston Technology Corporation)
• Inventors: Co, Ramon S., Lai, Tat Leung, Nguyen, Thang
• Primary Examiner(s): LE, DIEU MINH T
• Application Number:
  US09/702,018
• Time in Patent Office: 484 Days
• Field of Search: 714/42, 714/29, 714/54, 714/718, 714/767, 711/115, 711/170, 711/173, 710/102, 710/103
• US Class Current: 714/42
• CPC Class Codes: G01R 31/01 Subjecting similar articles in turn to test, e.g. "go/no-go" tests in mass production; Testing objects at points as they pass through a testing station testing of cables continuously passing the testing apparatus G01R31/59; testing dielectric strength or breakdown voltage G01R31/12
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56016 Apparatus features
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H05K 1/141 One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence

Abstract

Margin testing of memory modules uses a personal computer (PC) motherboard. A test adaptor board has a test socket that receives a memory module under test. Pins from the test adaptor board are plugged into holes of a removed memory-module socket on the motherboard, mounted on the reverse, solder side of the motherboard. The test adapter board has a voltage regulator that controls the power-supply (Vcc) voltage applied to the module under test. A delay circuit on the test adapter board varies the phase delay of a clock to the memory module under test. Margin control signals are generated by a controller card in the PC'"'"'s expansion slots, to control Vcc and clock delay to the module under test without changing the motherboard'"'"'s Vcc voltage. The test program executing on the PC motherboard writes to the controller card to adjust voltage and delay, allowing Vcc and setup and hold margins to be tested.

Claims

1. A test system for margin-testing memory modules comprising:

a motherboard, the motherboard being a main board for a computer using memory modules as a memory, the motherboard containing a processor for executing a test program that writes and reads memory;

a test adaptor board, mounted to the motherboard, the test adaptor board having a test socket for connecting memory modules for testing by the motherboard, the test adaptor board for electrically connecting a memory module connected to the test socket to the motherboard attached to the test adaptor board, the motherboard using the memory module inserted into the test socket as a portion of the memory of the motherboard; and

a voltage margin circuit, coupled between a power-supply and a power-supply input to the test socket, for adjusting a power-supply voltage applied to the memory module inserted into the test socket to a value that differs from the power-supply voltage on the motherboard by a voltage margin;

wherein the test program executing on the motherboard margin tests the memory module receiving a power-supply voltage that differs from the motherboard power-supply voltage by the voltage margin,

whereby margin testing of the memory module is performed without altering the power-supply voltage on the motherboard.

2. The test system of claim 1 wherein the test program alters the voltage margin during execution of the test program,

wherein the memory module is tested with at least two voltage margins by the test program,

whereby the voltage margin is adjusted under control of the test program.

3. The test system of claim 2 further comprising:

a test controller card, inserted into an expansion-bus slot on the motherboard, for generating a control signal to the voltage margin circuit, the control signal indicating a desired voltage margin to be generated by the voltage margin circuit.

4. The test system of claim 3 wherein the test program executes write instructions that write values to programmable registers on the test controller card, the programmable registers for generating the control signal to the voltage margin circuit,

whereby the test program adjusts the voltage margin by writing to the programmable registers.

5. The test system of claim 1 further comprising:

a delay margin circuit, coupled between a memory clock on the motherboard and a clock input to test socket for driving a memory clock to the memory module being tested, the delay margin circuit adjusting a phase delay of the memory clock to the test socket,

whereby the phase delay is adjusted for margin testing of the memory module.

6. The test system of claim 5 wherein the delay margin circuit comprises a phase-locked loop (PLL), delay buffers, and a mux for selecting an output from one of the delay buffers.

7. The test system of claim 5 wherein setup and hold times from address inputs to the test socket are adjusted by the phase delay of the memory clock adjusted by the delay margin circuit,

whereby address setup and hold margins are tested.

8. The test system of claim 7 wherein the delay margin circuit is mounted on the test adaptor board.

9. The test system of claim 7 wherein the delay margin circuit is a clock chip mounted on the motherboard, the clock chip also for generating a processor clock to the processor on the motherboard that executes the test program;

wherein the test program writes to the clock chip to adjust the memory clock to the test socket to adjust the phase delay.

10. The test system of claim 9 wherein the motherboard has a component side and a solder side, the component side having integrated circuits mounted thereon and expansion sockets for expansion boards;

wherein the test adaptor board is mounted above the solder side of the motherboard.

11. The test system of claim 10 further comprising:

pins coupled between the motherboard and the test adaptor board, the pins being mounted into holes on the motherboard for a removed memory-module socket;

wherein the power-supply voltage on the motherboard is coupled to the voltage margin circuit by at least one of the pins.

12. A method for margin testing memory modules using a motherboard-based tester comprising:

executing a test program on a motherboard;

specifying a first test power-supply voltage that differs from a nominal power-supply voltage on the motherboard by a first voltage margin;

applying the first test power-supply voltage to a memory module under test, the memory module under test being connected to a memory bus on the motherboard by a test adapter board with a test socket for connecting to the memory module under test;

the test program executing instructions to write to the memory module under test and to read from the memory module under test, when the memory module under test has the first test power-supply voltage applied;

specifying a second test power-supply voltage that differs from the nominal power-supply voltage on the motherboard by a second voltage margin, the second voltage margin differing from the first voltage margin;

applying the second test power-supply voltage to the memory module under test; and

the test program executing instructions to write to the memory module under test and to read from the memory module under test, when the memory module under test has the second test power-supply voltage applied,

whereby the memory module under test is tested at two different voltage margins.

13. The method of claim 12 further comprising:

specifying a first phase delay;

adjusting a phase delay of a control signal to the memory module under test in response to the first phase delay to generate a first delayed control signal;

applying the first delayed control signal to the memory module under test when the test program executes instructions to write to the memory module under test and to read from the memory module under test;

specifying a second phase delay;

adjusting the phase delay of the control signal to the memory module under test in response to the second phase delay to generate a second delayed control signal;

applying the second delayed control signal to the memory module under test when the test program executes instructions to write to the memory module under test and to read from the memory module under test,

whereby the memory module under test is tested at two different phase-delay margins.

14. The method of claim 13 wherein specifying the first and second phase delays comprises specifying the first and second phase delays to meet or exceed setup and hold time specifications of address, data, or other control signals to the memory module under test,

whereby setup and hold margins are tested.

15. The method of claim 14 wherein the test program executes instructions to write values to programmable registers to specify the first and second phase delays and the first and second test power-supply voltage,

whereby margins are changed under program control.

16. A memory-module margin tester comprising:

test adapter board means for electrically connecting to a memory module under test;

motherboard means for executing a test program means for testing the memory module under test, the motherboard means including expansion-bus means for accepting expansion cards, and memory means for storing data, the memory means including local memory means for storing data on the motherboard means, and a connection means for connecting the memory means to the memory module under test through the test adapter board means; and

voltage margin means, coupled to the test adapter board means, for varying a power-supply voltage to the memory module under test in response to the test program means, the voltage margin means not adjusting a power-supply voltage to the local memory means;

whereby the power-supply voltage to the memory module under test is varied in response to the test program means during margin testing.

17. The memory-module margin tester of claim 16 further comprising:

phase margin means, coupled to the test adapter board means, for varying a phase of a signal to the memory module under test in response to the test program means, the phase margin means not adjusting a phase of a signal to the local memory means;

whereby the phase to the memory module under test is varied in response to the test program means during margin testing.

18. The memory-module margin tester of claim 17 wherein the phase margin means comprises a phase-locked loop (PLL), the signal being a clock signal.

19. The memory-module margin tester of claim 18 wherein the test program means further comprises means for generating a select signal to the phase margin means, the select signal selecting a clock phase from among a plurality of clock phases generated by the phase margin means.

20. The memory-module margin tester of claim 19 wherein the memory module under test is a single-inline memory module SIMM or a dual-inline memory module DIMM or a RAMBUS module or a double-data rate (DDR) module.