Single transistor cell, method for manufacturing the same, memory circuit composed of single transistors cells, and method for driving the same

• US 6,352,864 B1
• Filed: 07/24/2000
• Issued: 03/05/2002
• Est. Priority Date: 12/31/1997
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jong-ho
• Primary Examiner(s): Lebentritt, Michael S.
• Assistant Examiner(s): Wilson, Christian D.
• Application Number:
  US09/624,398
• Time in Patent Office: 589 Days
• Field of Search: 257/295, 365/65, 365/145, 438/3
• US Class Current: 438/3
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 11/223 using MOS with ferroelectric gate insulating film
• CPC Class Codes: H01L 29/40111 the electrodes comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H01L 29/6684 with a ferroelectric gate insulator
• CPC Class Codes: H01L 29/78391 the gate comprising a layer which is used for its ferroelectric properties

Abstract

A semiconductor memory device, a method for manufacturing the same, a memory circuit including the semiconductor memory device, and a method for driving the same, are provided. In detail, one transistor forms a memory cell, and a single transistor cell capable of arbitrarily accessing the memory cell, a method for manufacturing the same, a memory circuit, and a method for driving the memory circuit, are provided. An island type semiconductor layer as an active region is formed on a ferroelectric layer. A word line crosses the semiconductor layer. A source is formed on the semiconductor layer on one side of the word line, and a drain is formed on the other side. A plate line is formed below the ferroelectric layer to face the word line, and intersects the word line. A drive line is connected to the source, and a bit line is connected to the drain.

Claims

1. A method for manufacturing a single transistor cell comprising:

(a) forming a rectangular plate line extending in a first direction, on a semiconductor substrate;

(b) forming a rectangular ferroelectric line extending in a second direction perpendicular to the first direction to cross the plate line, on the resultant structure where the plate line is formed;

(c) forming an island type semiconductor layer on the ferroelectric line in a region where the ferroelectric line overlaps the plate line;

(d) forming a rectangular word line extending in the second direction to cross the semiconductor layer; and

(e) forming source and drain regions in the semiconductor layer on opposite sides of the word line and over the region where the ferroelectric line overlaps the plate line.

2. The method of claim 1, wherein a reaction preventing layer is formed before forming the plate line, said reaction preventing layer suppressing reaction of the semiconductor substrate with the ferroelectric line.

3. The method of claim 2, wherein the reaction preventing layer is formed of TiO₂.

4. The method of claim 1, wherein forming the plate line further comprises:

depositing Pt on an entire top surface of the semiconductor substrate; and

photo etching the Pt to form the plate line extending in the first direction.

5. The method of claim 1, wherein forming the ferroelectric line further comprises:

depositing ferroelectric material on an entire top surface of a resultant structure where the plate line is formed, by a sol-gel coating method or a sputtering method; and

photo etching the ferroelectric material to form the ferroelectric line, extending in the second direction perpendicular to the first direction and crossing the plate line.

6. The method of claim 5, wherein the ferroelectric material is one selected from the group consisting of PZT, PLZT, PNZT, PbTiO₃ and Y1.

7. The method of claim 1, wherein forming the semiconductor layer further comprises:

forming SnO₂ on an entire top surface of a resultant structure where the ferroelectric line is formed, to produce a SnO₂ layer;

implanting in ions into the SnO₂ layer; and

photo etching the In-implanted SnO₂ layer to form an island type semiconductor layer in a region where the plate line overlaps the ferroelectric line.

8. The method of claim 1, wherein the semiconductor layer is formed of an oxide.

9. The method of claim 1, wherein forming the word line further comprises:

forming an oxide layer on an entire top surface of the substrate where a semiconductor layer is formed;

forming a conductive material on the oxide layer; and

photo etching the conductive material and the oxide layer to form the rectangular word line across the semiconductor layer.

10. The method of claim 1, further comprising forming a thin A1₂O₃ layer prior to forming the rectangular word line.

11. A method for manufacturing a single transistor cell, comprising (a) forming a rectangular late line extending in a first direction, on a semiconductor substrate, (b) forming a rectangular ferroelectric line extending in a second direction perpendicular to the first direction to cross the plate line, on the resultant structure where the plate line is formed, (c) forming an island type semiconductor layer on the ferroelectric line in a region where the ferroelectric line overlaps the plate line, and (d) forming a rectangular word line extending in the second direction to cross the semiconductor layer, wherein said method further comprises:

implanting impurity ions on an entire top surface of the substrate, to form a source on a first side of the word line, and a drain on a second side of the word line, on the semiconductor layer;

forming a first interdielectric layer on the entire top surface of the substrate;

selectively etching the first interdielectric layer to form a first contact window partially exposing the source;

forming a drive line connected to the source through the first contact window, on the first interdieletric layer;

forming a second interdiectric layer on the entire top surface of the substrate;

selectively etching the first and second interdielectric layers to form a second contact window partially exposing the drain; and

forming a bit line connected to the drain through the second contact window, on the second interdieletric layer.

12. The method of claim 11, wherein the drive line crosses the bit line.