Load capacitance measuring circuit and output buffer adaptive to wide range of load capacitance

• US 6,353,337 B2
• Filed: 12/19/2000
• Issued: 03/05/2002
• Est. Priority Date: 07/17/2000
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Adachi, Kiyoshi, Nasu, Koji
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Tan, Vibol
• Application Number:
  US09/739,246
• Publication Number:
  US 20020008543A1
• Time in Patent Office: 441 Days
• Field of Search: 326/83, 326/88, 327/143, 327/198, 324/678, 324/679, 324/676
• US Class Current: 326/83
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance

Abstract

An output buffer includes a reference capacitor; a constant current source connected in series with the reference capacitor, for generating a reference voltage with a constant gradient by charging the reference capacitor; a first transistor having its source connected to a capacitive load, and its gate connected to the connecting point of the reference capacitor and the first constant current source to be supplied with the reference voltage; a second transistor connected between the drain of the first transistor and a voltage source; a third transistor connected between the capacitive load and the voltage source; and a fourth transistor connected to the control terminal of the second transistor and to the control terminal of the third transistor, for switching the second and third transistors from an OFF state to an ON state when the first transistor is turned on. It solves a problem of a conventional output buffer in that when the load capacitance of an external circuit differs from a presupposed one, it cannot meet the specification of the slew rate, or can consume excessive power.

Claims

1. A load capacitance measuring circuit comprising:

a reference capacitor;

a constant current source connected in series with said reference capacitor, for generating a reference voltage with a constant gradient in said reference capacitor;

a load resistor; and

a transistor having its source connected to a capacitive load to be measured, its gate connected to a connecting point of said reference capacitor and said constant current source to be supplied with the reference voltage, and its drain connected to a voltage source via said load resistor, wherein

a capacitance of the capacitive load is obtained from the drain voltage of said transistor and the gradient of the reference voltage.

2. The load capacitance measuring circuit according to claim 1, wherein a capacitance of said reference capacitor is variable.

3. The load capacitance measuring circuit according to claim 1, wherein a constant current said constant current source outputs is variable.

4. An output buffer comprising:

a reference capacitor;

a first constant current source connected in series with said reference capacitor, for generating a reference voltage with a constant gradient by charging said reference capacitor;

a first transistor having its source connected to a capacitive load, and its gate connected to a connecting point of said reference capacitor and said first constant current source to be supplied with the reference voltage;

a first switching device connected between the drain of said first transistor and a voltage source;

a second switching device connected between the capacitive load and the voltage source; and

a first driver connected to a control terminal of said first switching device and to a control terminal of said second switching device, for switching said first switching device and said second switching device from an OFF state to an ON state when said first transistor is turned on.

5. The output buffer according to claim 4, further comprising:

a second constant current source connected in series with said reference capacitor, for changing the reference voltage at a constant rate by discharging said reference capacitor;

a second transistor having its source connected to the capacitive load, and its gate connected to a connecting point of said reference capacitor and said second constant current source to be supplied with the reference voltage;

a third switching device connected between the drain of said second transistor and a ground;

a fourth switching device connected between the capacitive load and the ground; and

a second driver connected to a control terminal of said third switching device and to a control terminal of said fourth switching device, for switching said third switching device and said fourth switching device from an OFF state to an ON state when said second transistor is turned on.

6. The output buffer according to claim 5, wherein a capacitance of said reference capacitor is variable.

7. The output buffer according to claim 5, wherein a constant current supplied from said first constant current source to said reference capacitor is variable.

8. The output buffer according to claim 5, wherein a constant current discharged from said reference capacitor by said second constant current source is variable.

9. An output buffer comprising:

a reference capacitor;

a first constant current source connected in series with said reference capacitor, for generating a reference voltage with a constant gradient by charging said reference capacitor;

a first transistor having its source connected to a capacitive load, and its gate connected to a connecting point of said reference capacitor and said first constant current source to be supplied with the reference voltage;

a first switching device connected between the drain of said first transistor and a voltage source;

a second switching device connected between the capacitive load and the voltage source; and

a third switching device that is connected between a control terminal of said first switching device and a control terminal of said second switching device, and controlled by a voltage across the capacitive load.

10. The output buffer according to claim 9, further comprising:

a second constant current source connected in series with said reference capacitor, for changing the reference voltage at a constant rate by discharging said reference capacitor;

a second transistor having its source connected to the capacitive load, and its gate connected to a connecting point of said reference capacitor and said second constant current source to be supplied with the reference voltage;

a fourth switching device connected between the drain of said second transistor and the ground;

a fifth switching device connected between the capacitive load and the ground; and

a sixth switching device that is connected between a control terminal of said fourth switching device and a control terminal of said fifth switching device, and controlled by the voltage across the capacitive load.

11. The output buffer according to claim 10, wherein a capacitance of said reference capacitor is variable.

12. The output buffer according to claim 10, wherein a constant current supplied from said first constant current source to said reference capacitor is variable.

13. The output buffer according to claim 10, wherein a constant current discharged from said reference capacitor by said second constant current source is variable.