Clock generator circuit
First Claim
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1. A clock generator circuit comprising:
- an oscillation circuit which generates a first clock signal;
a first timer which counts the first clock signal;
a ring oscillator which generates a second clock signal;
a second timer that receives an overflow signal of the first timer, and that counts the second clock signal; and
a third timer including a reload register for storing an inverted value of each bit of the second timer, counting the inverted value, and setting a count value of the second timer, the third timer generating a third clock signal.
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Abstract
A clock generator circuit includes an oscillation circuit which generates a first clock signal, a first timer which counts the first clock signal, a ring oscillator which generates a second clock signal, a second timer which counts the second clock signal, and a third timer that generates a third clock signal which is the output clock signal.
6 Citations
8 Claims
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1. A clock generator circuit comprising:
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an oscillation circuit which generates a first clock signal;
a first timer which counts the first clock signal;
a ring oscillator which generates a second clock signal;
a second timer that receives an overflow signal of the first timer, and that counts the second clock signal; and
a third timer including a reload register for storing an inverted value of each bit of the second timer, counting the inverted value, and setting a count value of the second timer, the third timer generating a third clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
a Schmidt circuit providing an input to the first clock signal and outputting a signal to the first timer; and
a latch circuit receiving an output signal of the Schmidt circuit and an overflow signal of the first timer and outputting a signal to the second timer.
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4. The clock generator circuit according to claim 1, wherein the first timer sets an optional count value.
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5. The clock generator circuit according to claim 2, wherein the fourth timer sets an optional count value.
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6. The clock generator circuit according to claim 2, wherein the first timer sets an optional count value.
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7. The clock generator circuit according to claim 3, wherein the first timer sets an optional count value.
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8. The clock generator circuit according to claim 3, wherein the fourth timer sets an optional count value.
Specification
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Current AssigneeMitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Mitsubishi Electric System (Mitsubishi Electric Corporation)
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Original AssigneeMitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
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InventorsAikawa, Minoru
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Primary Examiner(s)RUBIN, MARGARET R
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Application NumberUS09/855,512Time in Patent Office293 DaysField of Search327/298, 327/299, 327/114, 327/144, 327/291US Class Current327/291CPC Class CodesH03L 7/00 Automatic control of freque...
